From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id B2B413858020; Thu, 7 Oct 2021 19:54:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B2B413858020 From: "vmakarov at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/102627] [11/12 Regression] wrong code with "-O1" Date: Thu, 07 Oct 2021 19:54:25 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: ra, wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: vmakarov at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 11.3 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Oct 2021 19:54:25 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D102627 --- Comment #4 from Vladimir Makarov --- (In reply to Jakub Jelinek from comment #3) > The assembly difference r11-8007 to r11-8008 is: > --- pr102627.s 2021-10-06 06:32:46.000000000 -0400 > +++ pr102627.s 2021-10-06 06:33:00.000000000 -0400 > @@ -77,10 +77,10 @@ main: > movq %rdx, %rcx > movq %rax, %rdx > movq e(%rip), %rax > - movq %rcx, 8(%rsp) > + movl %ecx, 12(%rsp) > movzbl f(%rip), %ecx > salq %cl, %rax > - movq 8(%rsp), %rcx > + movl 12(%rsp), %ecx > movq %rax, %rsi > movl $0, %edi > call w > I believe y returns the 128-bit struct g return value in %rdx:%rax pair, > right before the above instructions, and the above change means that inst= ead > of spilling the whole 64-bits of %rcx that holds at that point u.j and u.k > members (u.k in the upper 32 bits of %rcx) it spills just 32-bits of %ecx > and fills it back in, effectively setting u.k to 0. The w call then takes > %rdi, %rsi arguments it doesn't use and the TImode in %rcx:%rdx pair, but > with the high 32 bits of the TImode value lost. The reason for the spill= is > clear, the shift instruction needs that register... Jakub, thank you for the analysis. I believe the patch in question just triggered a bug in hard reg live range splitting. I am working on the PR. I hope to fix it on this week or at begining of the next week.=