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From: "vmakarov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/102842] [10 Regression] ICE in cselib_record_set at -O2 or greater
Date: Thu, 21 Oct 2021 17:47:33 +0000 [thread overview]
Message-ID: <bug-102842-4-yulgoz9RvR@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-102842-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102842
--- Comment #12 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
The patch just hid the bug. I believe the bug is still present on the trunk
too.
The insn in question is
(insn 26 64 109 3 (parallel [
(set (reg:SI 134 [ _12 ])
(plus:SI (mult:SI (reg:SI 117 [ _8 ])
(reg:SI 128))
(reg:SI 138)))
(set (reg:SI 135 [ _12+4 ])
(plus:SI (truncate:SI (lshiftrt:DI (plus:DI (mult:DI
(zero_extend:DI (reg:SI 117 [ _8 ]))
(zero_extend:DI (reg:SI 128)))
(zero_extend:DI (reg:SI 138)))
(const_int 32 [0x20])))
(reg:SI 138)))
]) "a.cpp":15:32 70 {umlal}
(expr_list:REG_DEAD (reg:SI 138)
(expr_list:REG_DEAD (reg:SI 128)
(nil))))
And its definition is
(define_insn "<US>mlal"
[(set (match_operand:SI 0 "s_register_operand" "=r,&r")
(plus:SI
(mult:SI
(match_operand:SI 4 "s_register_operand" "%r,r")
(match_operand:SI 5 "s_register_operand" "r,r"))
(match_operand:SI 1 "s_register_operand" "0,0")))
(set (match_operand:SI 2 "s_register_operand" "=r,&r")
(plus:SI
(truncate:SI
(lshiftrt:DI
(plus:DI
(mult:DI (SE:DI (match_dup 4)) (SE:DI (match_dup 5)))
(zero_extend:DI (match_dup 1)))
(const_int 32)))
(match_operand:SI 3 "s_register_operand" "2,2")))]
"TARGET_32BIT"
"<US>mlal%?\\t%0, %2, %4, %5"
[(set_attr "type" "umlal")
(set_attr "predicable" "yes")
(set_attr "arch" "v6,nov6")]
After couple of LRA constraints and assignment sub-passes, the two output
operands get the same hard reg. And this results in cse abort in post-reload
pass.
The issue is that reload pseudos for pseudos 134 and 135 get the same value as
they both are matched with different occurrences of pseudo 138 in the insn.
The bug is in a very sensitive LRA code area and fixing it will take some time.
But I hope I'll have a fix at the end of next week.
next prev parent reply other threads:[~2021-10-21 17:47 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 14:43 [Bug other/102842] New: [10 Regression] ICE in cselib_record_set at 02 " herrtimson at yahoo dot de
2021-10-19 14:43 ` [Bug other/102842] " herrtimson at yahoo dot de
2021-10-19 14:50 ` marxin at gcc dot gnu.org
2021-10-19 14:55 ` herrtimson at yahoo dot de
2021-10-19 18:36 ` [Bug rtl-optimization/102842] " pinskia at gcc dot gnu.org
2021-10-19 18:43 ` [Bug rtl-optimization/102842] [10/11/12 " pinskia at gcc dot gnu.org
2021-10-20 8:28 ` [Bug rtl-optimization/102842] [10 Regression] ICE in cselib_record_set at -O2 " marxin at gcc dot gnu.org
2021-10-20 10:46 ` marxin at gcc dot gnu.org
2021-10-20 10:46 ` marxin at gcc dot gnu.org
2021-10-20 11:32 ` herrtimson at yahoo dot de
2021-10-20 12:19 ` marxin at gcc dot gnu.org
2021-10-20 15:29 ` herrtimson at yahoo dot de
2021-10-21 7:25 ` marxin at gcc dot gnu.org
2021-10-21 12:35 ` herrtimson at yahoo dot de
2021-10-21 17:47 ` vmakarov at gcc dot gnu.org [this message]
2021-10-26 19:17 ` cvs-commit at gcc dot gnu.org
2021-10-30 10:32 ` [Bug rtl-optimization/102842] [10/11/12 " herrtimson at yahoo dot de
2021-11-03 17:47 ` cvs-commit at gcc dot gnu.org
2021-11-03 17:48 ` cvs-commit at gcc dot gnu.org
2021-11-05 13:51 ` rguenth at gcc dot gnu.org
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