From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
 id 19A10385801F; Mon, 22 Nov 2021 18:18:34 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 19A10385801F
From: "jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/103074] [11/12 Regression] ICE in lra_assign, at
 lra-assigns.c:1649 since r11-5066-gbe39636d9f68c437
Date: Mon, 22 Nov 2021 18:18:33 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 12.0
X-Bugzilla-Keywords: ice-on-valid-code
X-Bugzilla-Severity: normal
X-Bugzilla-Who: jakub at gcc dot gnu.org
X-Bugzilla-Status: NEW
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P2
X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org
X-Bugzilla-Target-Milestone: 11.3
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-103074-4-qMV7CUs9or@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-103074-4@http.gcc.gnu.org/bugzilla/>
References: <bug-103074-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
X-BeenThere: gcc-bugs@gcc.gnu.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: Gcc-bugs mailing list <gcc-bugs.gcc.gnu.org>
List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-bugs>,
 <mailto:gcc-bugs-request@gcc.gnu.org?subject=unsubscribe>
List-Archive: <https://gcc.gnu.org/pipermail/gcc-bugs/>
List-Post: <mailto:gcc-bugs@gcc.gnu.org>
List-Help: <mailto:gcc-bugs-request@gcc.gnu.org?subject=help>
List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-bugs>,
 <mailto:gcc-bugs-request@gcc.gnu.org?subject=subscribe>
X-List-Received-Date: Mon, 22 Nov 2021 18:18:34 -0000

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103074

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Ah, actually what I see is that sched1 swaps the order of:
(insn 22 21 23 4 (parallel [
            (set (reg:SI 88)
                (ashiftrt:SI (reg/v:SI 84 [ a ])
                    (const_int 32 [0x20])))
            (clobber (reg:CC 17 flags))
        ]) "pr103074.c":10:7 735 {*ashrsi3_1}
     (expr_list:REG_UNUSED (reg:CC 17 flags)
        (nil)))
(insn 23 22 24 4 (set (reg:SI 2 cx)
        (reg/v:SI 84 [ a ])) "pr103074.c":10:7 77 {*movsi_internal}
     (expr_list:REG_DEAD (reg/v:SI 84 [ a ])
        (nil)))
and doing a shift when cx is live isn't an option because the shift needs t=
he
hard register for this shift amount (the constraints are Ic and I is 0..31
constant, c is %cx register).=