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From: "tnfchris at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/103094] New: [12 Regression] Incorrect codegen from
 AArch64 intrinsics
Date: Fri, 05 Nov 2021 09:50:07 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103094

            Bug ID: 103094
           Summary: [12 Regression] Incorrect codegen from AArch64
                    intrinsics
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Keywords: wrong-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: tnfchris at gcc dot gnu.org
  Target Milestone: ---
            Target: aarch64-*

The following testcase

---

#include <arm_neon.h>

void foo (uint8x8x2_t cols_01_23, uint8x8x2_t cols_45_67, uint16_t* outptr0)
{
  uint16x4x4_t cols_01_23_45_67 =3D { {
    vreinterpret_u16_u8(cols_01_23.val[0]),
    vreinterpret_u16_u8(cols_01_23.val[1]),
    vreinterpret_u16_u8(cols_45_67.val[0]),
    vreinterpret_u16_u8(cols_45_67.val[1])
  } };

  vst4_lane_u16(outptr0, cols_01_23_45_67, 0);
}

---

Causes incorrect codegen

```
foo:
        mov     v4.8b, v0.8b
        mov     v5.8b, v1.8b
        mov     v6.8b, v1.8b
        mov     v7.8b, v2.8b
        st4     {v4.h - v7.h}[0], [x0]
        ret
```

as the same register `v1` is used as source for two inputs.

This happens in cprop_hardreg where a correct RTL

```
(insn 20 37 26 2 (set (reg:V4HI 61 v29 [ __val+8 ])
        (reg:V4HI 36 v4 [ cols_01_23+8 ])) 1158 {*aarch64_simd_movv4hi}
     (nil))
```

is turned into

```
(insn 20 37 26 2 (set (reg:V4HI 61 v29 [ __val+8 ])
        (reg:V4HI 33 v1 [orig:36 cols_01_23+8 ] [36])) 1158
{*aarch64_simd_movv4hi}
     (nil))
```

which is a bogus transform as `v1` is still live and pointing to `cols_45_6=
7`.

started somewhere between g:4096eb50d108a9ccef134f2e891c751b1cc9f6b2 and
g:29a1af24eface3620e348be9429e7c2e872accbc=