From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 6CB0E3857809; Tue, 16 Nov 2021 02:39:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6CB0E3857809 From: "hjl.tools at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/103194] [12 Regression] ice in optimize_atomic_bit_test_and with __sync_fetch_and_and since r12-5102-gfb161782545224f5 Date: Tue, 16 Nov 2021 02:39:46 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: blocker X-Bugzilla-Who: hjl.tools at gmail dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P1 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 12.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Nov 2021 02:39:46 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103194 --- Comment #16 from H.J. Lu --- (In reply to Hongtao.liu from comment #15) > (In reply to H.J. Lu from comment #13) > > (In reply to Hongtao.liu from comment #8) > > > unsigned long pscc_a_2_3; > > > int pscc_a_1_4; > > > unsigned long pc2; > > > void pscc(int n) > > > { > > > long mask =3D 1ll << n; > > > pc2 =3D __sync_fetch_and_or(&pscc_a_2_3, mask) & mask; > > > } > > >=20 > > > void pscc1(int n) > > > { > > > long mask =3D 1ll << 65; > > > pc2 =3D __sync_fetch_and_or(&pscc_a_2_3, mask) & mask; > > > } > > >=20 > > > pscc and pscc1 have different behavior when n >=3D 64, It seems unsaf= e to > > > optimize variable mask? > >=20 > > Is the behavior well defined for n >=3D 64? I got > >=20 > > foo.c:11:19: warning: left shift count >=3D width of type > > [-Wshift-count-overflow] > > 11 | long mask =3D 1ll << 65; > > | ^~ > According to C99 > The result of E1 << E2 is E1 left-shifted E2 bit positions; vacated bits = are > =EF=AC=81lled with zeros. If E1 has an unsigned type, the value of the re= sult is E1 > =C3=97 2E2, reduced modulo one more than the maximum value representable = in the > result type. If E1 has a signed type and nonnegative value, and E1 =C3=97= 2E2 is > representable in the result type, then that is the resulting value; > otherwise, the behavior is unde=EF=AC=81ned. >=20 > So yes, it's well defined, and the result is zero. This is the existing behavior since GCC 7.=