[Bug target/103196] New: [12 regression] gcc.target/powerpc/p9-vec-length-full-7.c

["seurer at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103196

            Bug ID: 103196
           Summary: [12 regression]
                    gcc.target/powerpc/p9-vec-length-full-7.c
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: seurer at gcc dot gnu.org
  Target Milestone: ---

g:8ed62c929c7c44627f41627e085e15d77b2e6ed4, r12-5129
make  -k check-gcc
RUNTESTFLAGS="powerpc.exp=gcc.target/powerpc/p9-vec-length-full-7.c"
FAIL: gcc.target/powerpc/p9-vec-length-full-7.c scan-assembler-times
\\mstxvl\\M 12
# of expected passes            1
# of unexpected failures        1

This was run on a power 9 but it fails on others, too.


commit 8ed62c929c7c44627f41627e085e15d77b2e6ed4 (HEAD, refs/bisect/bad)
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Wed Nov 10 15:58:15 2021 +0000

    middle-end: Add an RPO pass after successful vectorization

There used to be 12 stxvl instructions and now there are 14.  There are a bunch
of other changes and I am not sure if the new code is better or worse or if the
test case instruction count just needs updating.

seurer@marlin:~/gcc/git/build/gcc-test$ diff p9-vec-length-full-7.s.r12-5129
p9-vec-length-full-7.s.r12-5128
16c16
(the interesting parts...)
32,46c32,63
<       li 10,11
<       addi 7,6,16
<       addi 8,6,32
<       addi 6,6,48
<       addi 3,3,.LC0@toc@l
<       addi 4,4,.LC1@toc@l
<       addi 5,5,.LC2@toc@l
<       sldi 9,9,56
<       sldi 10,10,56
<       lxv 11,0(3)
<       lxv 12,0(4)
<       lxv 0,0(5)
<       stxvl 11,7,9
<       stxvl 12,8,9
<       stxvl 0,6,10
---
> 	li 3,43
> 	li 4,16
> 	addi 8,8,.LC0@toc@l
> 	vaddubm 1,1,1
> 	lxv 32,0(8)
> .L3:
> 	cmpldi 0,10,43
> 	sldi 7,9,56
> 	xxlor 0,32,32
> 	add 8,5,10
> 	vaddubm 0,0,1
> 	isel 9,3,10,1
> 	cmpldi 0,10,42
> 	addi 10,10,16
> 	stxvl 0,8,7
> 	subfic 9,9,43
> 	cmpldi 7,9,16
> 	isel 9,4,9,29
> 	bgtlr 0
> 	cmpldi 0,10,43
> 	sldi 7,9,56
> 	xxlor 0,32,32
> 	add 8,5,10
> 	vaddubm 0,0,1
> 	isel 9,3,10,1
> 	cmpldi 0,10,42
> 	addi 10,10,16
> 	stxvl 0,8,7
> 	subfic 9,9,43
> 	cmpldi 7,9,16
> 	isel 9,4,9,29
> 	ble 0,.L3
64,65c81
<       addis 6,2,.LANCHOR0@toc@ha
<       addis 8,2,.LANCHOR0+64@toc@ha
---
> 	addis 5,2,.LANCHOR0+64@toc@ha
67,68c83,84
<       addi 6,6,.LANCHOR0@toc@l
<       addi 8,8,.LANCHOR0+64@toc@l
---
> 	addi 5,5,.LANCHOR0+64@toc@l
> 	mr 8,5
70c86
< .L6:
---
> .L9:
76,79c92,95
<       bne 0,.L6
<       addis 3,2,.LC0@toc@ha
<       addis 4,2,.LC1@toc@ha
<       addis 5,2,.LC2@toc@ha
---
> 	bne 0,.L9
> 	addis 8,2,.LC0@toc@ha
> 	xxspltib 33,8
> 	li 10,16
81,95c97,128
<       li 10,11
<       addi 7,6,80
<       addi 8,6,96
<       addi 6,6,112
<       addi 3,3,.LC0@toc@l
<       addi 4,4,.LC1@toc@l
<       addi 5,5,.LC2@toc@l
<       sldi 9,9,56
<       sldi 10,10,56
<       lxv 11,0(3)
<       lxv 12,0(4)
<       lxv 0,0(5)
<       stxvl 11,7,9
<       stxvl 12,8,9
<       stxvl 0,6,10
---
> 	li 3,43
> 	li 4,16
> 	addi 8,8,.LC0@toc@l
> 	vaddubm 1,1,1
> 	lxv 32,0(8)
> .L10:
> 	cmpldi 0,10,43
> 	sldi 7,9,56
> 	xxlor 0,32,32
> 	add 8,5,10
> 	vaddubm 0,0,1
> 	isel 9,3,10,1
> 	cmpldi 0,10,42
> 	addi 10,10,16
> 	stxvl 0,8,7
> 	subfic 9,9,43
> 	cmpldi 7,9,16
> 	isel 9,4,9,29
> 	bgtlr 0
> 	cmpldi 0,10,43
> 	sldi 7,9,56
> 	xxlor 0,32,32
> 	add 8,5,10
> 	vaddubm 0,0,1
> 	isel 9,3,10,1
> 	cmpldi 0,10,42
> 	addi 10,10,16
> 	stxvl 0,8,7
> 	subfic 9,9,43
> 	cmpldi 7,9,16
> 	isel 9,4,9,29
> 	ble 0,.L10