From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 812453858412; Wed, 24 Nov 2021 05:47:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 812453858412 From: "crazylht at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/103252] questionable codegen with kmovd Date: Wed, 24 Nov 2021 05:47:50 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 11.2.0 X-Bugzilla-Keywords: missed-optimization, ra X-Bugzilla-Severity: normal X-Bugzilla-Who: crazylht at gmail dot com X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 24 Nov 2021 05:47:50 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103252 --- Comment #14 from Hongtao.liu --- (In reply to Hongtao.liu from comment #13) > >=20 > > So for short live range reg, we may lose opportunity to allocate best > > regclass, maybe add peephole2 to handle those cases instead of tune RA. > No, r132 is also used as addr, but currently lra only add cost of movement > from mask to gpr, but we could possibly run out of gpr which means there > will be an extra spill, and this is not counted by record_address_regs. >=20 > modified gcc/ira-costs.c > @@ -1226,7 +1226,7 @@ record_address_regs (machine_mode mode, addr_space_t > as, rtx x, > struct costs *pp; > int *pp_costs; > enum reg_class i; > - int k, regno, add_cost; > + int k, regno, add_cost, potential_spill_cost; > cost_classes_t cost_classes_ptr; > enum reg_class *cost_classes; > move_table *move_in_cost; > @@ -1239,6 +1239,7 @@ record_address_regs (machine_mode mode, addr_space_t > as, rtx x, > ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map[regno]) =3D true; > pp =3D COSTS (costs, COST_INDEX (regno)); > add_cost =3D (ira_memory_move_cost[Pmode][rclass][1] * scale) / 2; > + potential_spill_cost =3D add_cost / 5; > if (INT_MAX - add_cost < pp->mem_cost) > pp->mem_cost =3D INT_MAX; > else > @@ -1252,6 +1253,10 @@ record_address_regs (machine_mode mode, addr_space= _t > as, rtx x, > { > i =3D cost_classes[k]; > add_cost =3D (move_in_cost[i][rclass] * scale) / 2; > + /* If we run out of rclass regs, there could be an extra spill, > + Let's say 20% possibility. */ > + if (!ira_class_subset_p[i][rclass]) > + add_cost +=3D potential_spill_cost; > if (INT_MAX - add_cost < pp_costs[k]) > pp_costs[k] =3D INT_MAX; Increase cost will lose some spill to mask opportunity like testcase https://gcc.godbolt.org/z/KG63ErzEr=