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From: "jason at zx2c4 dot com" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/103252] questionable codegen with kmovd
Date: Tue, 16 Nov 2021 12:06:23 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103252

--- Comment #9 from Jason A. Donenfeld <jason at zx2c4 dot com> ---
>  When the mask registers are available for use, RA considers them and whe=
n spilling to those is cheaper than to memory, it spills to them and not me=
mory.

Yes, this is the thing I don't get. When you compare the codegen for avx512=
 vs
non-avx512, the non-avx512 doesn't spill at all there. So this isn't "spill=
 to
memory" vs "spill to mask register". This is "don't spill" vs "spill to mask
register". And the latter seems clearly worse.


-------------

(As an aside, Agner reports a certain "fast forwarding" on Tigerlake+, with
zero latency write-to-read for certain addresses, with stack computations b=
eing
easy ones. Looking at 'MOV r32,[m32]+MOV [m32],r32' here:=20
http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00506E3_Skylake2_In=
stLatX64.txt
http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00606A6_ICX_InstLat=
X64.txt
http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00806C1_TigerLake3_=
InstLatX64.txt
http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel0090672_AlderLake_B=
C_AVX512_InstLatX64.txt
you can see the huge reduction on Tigerlake and Alderlake. This is totally
irrelevant and immaterial for the purposes of this bug report, but I idly
wonder if at some point there'll be a slightly different cost model for this
between Icelake and Tigerlake+.)=