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From: "qinzhao at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/103271] ICE in assign_stack_temp_for_type with -ftrivial-auto-var-init=pattern and VLAs and -mno-strict-align on riscv64
Date: Thu, 02 Dec 2021 22:19:37 +0000	[thread overview]
Message-ID: <bug-103271-4-2z46REKTEW@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-103271-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103271

--- Comment #17 from qinzhao at gcc dot gnu.org ---
(In reply to Richard Biener from comment #12)
> diff --git a/gcc/internal-fn.c b/gcc/internal-fn.c
> index 6ac3460d538..08f94b7a17a 100644
> --- a/gcc/internal-fn.c
> +++ b/gcc/internal-fn.c
> @@ -3050,6 +3050,23 @@ expand_DEFERRED_INIT (internal_fn, gcall *stmt)
>         lhs_base = TREE_OPERAND (lhs_base, 0);
>        reg_lhs = (mem_ref_refers_to_non_mem_p (lhs_base)
>                  || non_mem_decl_p (lhs_base));
> +      /* If this expands to a register and the underlying decl is wrapped in
> +        a MEM_REF that just serves as an access type change expose the decl
> +        if it is of correct size.  This avoids a situation as in PR103271
> +        if the target does not support a direct move to the registers mode.
> */
> +      if (reg_lhs
> +         && TREE_CODE (lhs_base) == MEM_REF
> +         && TREE_CODE (TREE_OPERAND (lhs_base, 0)) == ADDR_EXPR
> +         && DECL_P (TREE_OPERAND (TREE_OPERAND (lhs_base, 0), 0))
> +         && integer_zerop (TREE_OPERAND (lhs_base, 1))
> +         && tree_fits_uhwi_p (var_size)
> +         && tree_int_cst_equal
> +              (var_size,
> +               DECL_SIZE_UNIT (TREE_OPERAND (TREE_OPERAND (lhs_base, 0),
> 0))))
> +       {
> +         lhs = TREE_OPERAND (TREE_OPERAND (lhs_base, 0), 0);
> +         var_type = TREE_TYPE (lhs);
> +       }
>      }
>  
>    if (!reg_lhs)
> 
> solves the issue.  There might be a situation where that's not enough though,
> I'm giving the above some testing.
this patch is so specific to target this specific case, I am wondering whether
this is needed if Tim will provide a patch to support MOVTI in riscv backend?

  parent reply	other threads:[~2021-12-02 22:19 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-16  8:55 [Bug target/103271] New: ICE in assign_stack_temp_for_type, at function.c:798 marxin at gcc dot gnu.org
2021-11-16  8:55 ` [Bug target/103271] " marxin at gcc dot gnu.org
2021-11-16  9:39 ` rguenth at gcc dot gnu.org
2021-11-22 23:17 ` [Bug target/103271] ICE in assign_stack_temp_for_type with -ftrivial-auto-var-init=pattern and VLAs and -mno-strict-align on riscv64 qinzhao at gcc dot gnu.org
2021-11-23  7:33 ` marxin at gcc dot gnu.org
2021-11-23  7:47 ` rguenther at suse dot de
2021-11-23 16:22 ` qing.zhao at oracle dot com
2021-11-26  5:08 ` wilson at gcc dot gnu.org
2021-11-26  5:20 ` wilson at gcc dot gnu.org
2021-11-26  7:16 ` rguenther at suse dot de
2021-12-01 17:17 ` qinzhao at gcc dot gnu.org
2021-12-01 19:46 ` qinzhao at gcc dot gnu.org
2021-12-01 22:31 ` qinzhao at gcc dot gnu.org
2021-12-02  9:07 ` rguenth at gcc dot gnu.org
2021-12-02  9:29 ` rguenth at gcc dot gnu.org
2021-12-02 12:35 ` cvs-commit at gcc dot gnu.org
2021-12-02 12:36 ` rguenth at gcc dot gnu.org
2021-12-02 16:12 ` qinzhao at gcc dot gnu.org
2021-12-02 17:47 ` wilson at gcc dot gnu.org
2021-12-02 22:19 ` qinzhao at gcc dot gnu.org [this message]
2021-12-03 23:08 ` wilson at gcc dot gnu.org

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