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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/103271] ICE in assign_stack_temp_for_type with
 -ftrivial-auto-var-init=pattern and VLAs and -mno-strict-align on riscv64
Date: Thu, 02 Dec 2021 09:07:47 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103271

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ebotcazou at gcc dot gnu.o=
rg,
                   |                            |law at gcc dot gnu.org

--- Comment #11 from Richard Biener <rguenth at gcc dot gnu.org> ---
(In reply to qinzhao from comment #10)
> looks like that this is exactly the same issue as exposed in pr102285.
>=20
> and the original fix to pr102285 just hide this inconsistent IR issue.
>=20
> -mno-strict-align exposed this issue again.
>=20
> So. I believe that we need to fix the inconsistent IR issue in order to
> completely resolve this issue.

The issue is simply that using build_zero_cst is "wrong" here in the sense
that we know the size is constant but we hide that fact.

In fact, C disallows initializing variable-sized objects, so an adjusted
testcase with

 int fb[tw] =3D {};

is not valid C.  I think the situation with risc-v is unfortunate since
all other places in the compiler that zero non-memory simply use
emit_move_insn from CONST0_RTX but that's not avilable since we do not
go the "correct" path only because have_insn_for (SET, TImode) does not
exist.

But I'm not a target / RTL expert enough to tell whether that's a general
problem that should be fixed.

I also have no idea how to manually generate a proper zeroing sequence
for the (reg:TI ..) pseudo the VLA typed aggregate expands to.

I suppose assigning TImode to a decl but not even being able to move TImode
can be a problem elsewhere...=