From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 3A7393858C27; Wed, 17 Nov 2021 02:15:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3A7393858C27 From: "rjiejie at me dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/103296] New: Select satisfied register for deleting noop move instruction. Date: Wed, 17 Nov 2021 02:15:21 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 10.2.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: rjiejie at me dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Nov 2021 02:15:21 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103296 Bug ID: 103296 Summary: Select satisfied register for deleting noop move instruction. Product: gcc Version: 10.2.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: rtl-optimization Assignee: unassigned at gcc dot gnu.org Reporter: rjiejie at me dot com Target Milestone: --- I found this case in my riscv vector test case, and following is snippets of problematic RTL: before register renamer : =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D (insn 64 62 109 4 (parallel [ (set (reg:VNx32HI 104 v8 [orig:148 _30 ] [148]) (unspec:VNx32HI [ (plus:VNx32HI (reg:VNx32HI 100 v4 [orig:149 _31 ] [149]) (zero_extend:VNx32HI (reg:VNx32QI 108 v12 [orig= :159 _41 ] [159]))) (reg:SI 66 vl) ] UNSPEC_USEVL)) (use (reg:VNx32QI 67 vtype)) ]) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":186= 5:1 23384 {*wadduvnx32qi_wv_nosetvl} (nil)) (insn 109 64 67 4 (set (reg:VNx32HI 100 v4 [orig:147 _29 ] [147]) (reg:VNx32HI 104 v8 [orig:148 _30 ] [148])) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":281= 5:1 21247 {*movvnx32hi} (nil)) (insn 67 109 69 4 (parallel [ (set (reg:VNx32HI 100 v4 [orig:147 _29 ] [147]) (unspec:VNx32HI [ (plus:VNx32HI (mult:VNx32HI (zero_extend:VNx32HI (vec_duplicate:VNx32QI (reg:QI 10 a0 [184]))) (zero_extend:VNx32HI (reg:VNx32QI 98 v2 [orig:152 _34 ] [152]))) (reg:VNx32HI 100 v4 [orig:147 _29 ] [147])) (reg:SI 66 vl) ] UNSPEC_USEVL)) (use (reg:VNx32QI 67 vtype)) ]) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":281= 5:1 27941 {*umaddvnx32qivnx32hi4_scalar_nosetvl} (expr_list:REG_EQUAL (unspec:VNx32HI [ (plus:VNx32HI (mult:VNx32HI (zero_extend:VNx32HI (reg:VNx32= QI 98 v2 [orig:152 _34 ] [152])) (const_vector:VNx32HI [ (const_int 2 [0x2]) ])) (reg:VNx32HI 104 v8 [orig:148 _30 ] [148])) (reg:SI 66 vl) ] UNSPEC_USEVL) (nil))) after register renamer : =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D (insn 64 62 109 4 (parallel [ (set (reg:VNx32HI 100 v4 [orig:148 _30 ] [148]) (unspec:VNx32HI [ (plus:VNx32HI (reg:VNx32HI 116 v20 [orig:149 _31 ] [149]) (zero_extend:VNx32HI (reg:VNx32QI 108 v12 [orig= :159 _41 ] [159]))) (reg:SI 66 vl) ] UNSPEC_USEVL)) (use (reg:VNx32QI 67 vtype)) ]) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":186= 5:1 23384 {*wadduvnx32qi_wv_nosetvl} (expr_list:REG_DEAD (reg:VNx32QI 108 v12 [orig:159 _41 ] [159]) (expr_list:REG_DEAD (reg:VNx32HI 100 v4 [orig:149 _31 ] [149]) (nil)))) (insn:TI 109 64 67 4 (set (reg:VNx32HI 124 v28 [orig:147 _29 ] [147]) (reg:VNx32HI 100 v4 [orig:148 _30 ] [148])) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":281= 5:1 21247 {*movvnx32hi} (expr_list:REG_DEAD (reg:VNx32HI 104 v8 [orig:148 _30 ] [148]) (nil))) (insn 67 109 69 4 (parallel [ (set (reg:VNx32HI 124 v28 [orig:147 _29 ] [147]) (unspec:VNx32HI [ (plus:VNx32HI (mult:VNx32HI (zero_extend:VNx32HI (vec_duplicate:VNx32QI (reg:QI 10 a0 [184]))) (zero_extend:VNx32HI (reg:VNx32QI 114 v18 [orig:152 _34 ] [152]))) (reg:VNx32HI 124 v28 [orig:147 _29 ] [147])) (reg:SI 66 vl) ] UNSPEC_USEVL)) (use (reg:VNx32QI 67 vtype)) ]) "/$GCC/lib/gcc/riscv64-unknown-linux-gnu/10.2.0/include/riscv_vector.h":281= 5:1 27941 {*umaddvnx32qivnx32hi4_scalar_nosetvl} (expr_list:REG_DEAD (reg:VNx32HI 104 v8 [orig:148 _30 ] [148]) (expr_list:REG_DEAD (reg:VNx32QI 98 v2 [orig:152 _34 ] [152]) (expr_list:REG_DEAD (reg:VNx32QI 98 v2 [orig:152 _34 ] [152]) (expr_list:REG_EQUAL (unspec:VNx32HI [ (plus:VNx32HI (mult:VNx32HI (zero_extend:VNx32HI (reg:VNx32QI 98 v2 [orig:152 _34 ] [152])) (const_vector:VNx32HI [ (const_int 2 [0x2]) ])) (reg:VNx32HI 104 v8 [orig:148 _30 ] [148])) (reg:SI 66 vl) ] UNSPEC_USEVL) (nil)))))) >>From rnreg pass RTL dump as following, it will try to tie chains in a move instruction for a single output. So we can keep same register (dest and source) in this move instruction, it means insn 64 renamed as v4, and insn 109 should keep v4 as noop move instruction. Register v8 in insn 64deferring rescan insn with uid =3D 64. deferring rescan insn with uid =3D 109. , renamed as v4 Register v4 in insn 109deferring rescan insn with uid =3D 109. deferring rescan insn with uid =3D 67. deferring rescan insn with uid =3D 69. , renamed as v28=