From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id A31A93858439; Fri, 26 Nov 2021 11:37:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A31A93858439 From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug middle-end/103393] [12 Regression] Generating 256bit register usage with -mprefer-avx128 -mprefer-vector-width=128 Date: Fri, 26 Nov 2021 11:37:13 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: middle-end X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P1 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 12.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Nov 2021 11:37:13 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103393 --- Comment #16 from Jakub Jelinek --- (In reply to Richard Earnshaw from comment #15) > It seems perverse to me that you have a standard named pattern in the x86 > backend that is enabled, but then you somehow expect the generic parts of > the compiler to know that it shouldn't be used. They should be used, but only if the user code asks for it explicitly. So, say a 32-byte generic vector in user code, or the intrins= ics that need 32-byte vectors are just fine. The option just asks that the compiler tries hard not to introduce those on= its own (e.g. vectorization but this string ops expansion is similar to that). With those selected ISAs, such instructions are available, but on some CPUs= use of those is not really performance beneficial and using smaller vectors mig= ht get better results.=