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Subject: [Bug target/103396] [12 Regression][GCN][BUILD] ICE RTL check:
 access of elt 4 of vector with last elt 3 in move_callee_saved_registers, at
 config/gcn/gcn.c:2821
Date: Thu, 25 Nov 2021 16:05:40 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103396

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Andrew Stubbs <ams@gcc.gnu.org>:

https://gcc.gnu.org/g:58d50a5dd6344179eebaeb6fd2f895e59463cf74

commit r12-5525-g58d50a5dd6344179eebaeb6fd2f895e59463cf74
Author: Andrew Stubbs <ams@codesourcery.com>
Date:   Thu Nov 25 15:59:20 2021 +0000

    amdgcn: Fix ICE generating CFI [PR103396]

    gcc/ChangeLog:

            PR target/103396
            * config/gcn/gcn.c (move_callee_saved_registers): Ensure that t=
he
            number of spilled registers is counted correctly.=