[Bug translation/103482] New: Unnecessary ANDI instruction is generated for MIPS target

[Bug translation/103482] New: Unnecessary ANDI instruction is generated for MIPS target

[yuri.karlsbrun at broadcom dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103482

            Bug ID: 103482
           Summary: Unnecessary ANDI instruction is generated for MIPS
                    target
           Product: gcc
           Version: og10 (devel/omp/gcc-10)
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: translation
          Assignee: unassigned at gcc dot gnu.org
          Reporter: yuri.karlsbrun at broadcom dot com
  Target Milestone: ---

Created attachment 51903
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=51903&action=edit
Generated assembly file

There is unnecessary (useless) instruction ADDI is generated after the LHU
instruction.

GCC configuration and version:
Target: mipsisa32-elf
Configured with: ../configure --enable-languages=c,c++ --target=mipsisa32-elf
----with-float=soft --with-newlib --with-gnu-as --with-gnu-ld --disable-shared
--disable-libssp
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 10.3.0 20210408 (GCC) 

Command line:
$ mipsisa32-elf-gcc -Os -fcommon -fomit-frame-pointer -ffunction-sections      
-frename-registers -fweb -fno-builtin -c -o andi.o andi.c -v -save-temps
-msoft-float


Source file addi.c:

unsigned short cF;
unsigned short tC;

unsigned int  func(void)
{
  unsigned int totCell;

  unsigned short cellFill = cF;
  totCell = tC; 
  totCell = ((totCell & 0xFF) << 8) | (totCell >> 8);
  return totCell*cellFill;
}

Disassembled object file andi.o:
andi.o:     file format elf32-bigmips


Disassembly of section .text.func:

00000000 <func>:
   0:   97820000        lhu     v0,0(gp)
   4:   97880000        lhu     t0,0(gp)
   8:   3044ffff        andi    a0,v0,0xffff ## unnecessary clearing upper bits
                                             ## lhu does not do sign extension 
   c:   00021a00        sll     v1,v0,0x8
  10:   00042a02        srl     a1,a0,0x8
  14:   00653025        or      a2,v1,a1
  18:   30c7ffff        andi    a3,a2,0xffff
  1c:   03e00008        jr      ra
  20:   70e81002        mul     v0,a3,t0