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* [Bug target/103568] New: sub-optimal vector construction with two loaded doubles on Power10
@ 2021-12-06  2:05 linkw at gcc dot gnu.org
  2021-12-06 11:43 ` [Bug target/103568] " segher at gcc dot gnu.org
  2021-12-06 11:43 ` segher at gcc dot gnu.org
  0 siblings, 2 replies; 3+ messages in thread
From: linkw at gcc dot gnu.org @ 2021-12-06  2:05 UTC (permalink / raw)
  To: gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103568

            Bug ID: 103568
           Summary: sub-optimal vector construction with two loaded
                    doubles on Power10
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: linkw at gcc dot gnu.org
  Target Milestone: ---

For the test case:

vector double test(double *a, double *b) {
  return (vector double) { *a, *b };
}

On Power10, we generate the code like:

        ld 10,0(3)
        ld 9,0(4)
        mtvsrdd 34,9,10

As Power10 latency table, we can get better code with xxlor like:

        lxsd 0, 0(4)
        lxvrdx 1, 0, 3
        xxlor 34, 1, 32

As to the prerequisites "if we can assume the doubleword 1 of a vsx register
after an lfd is zero", as Segher pointed out "ISA 3.1 section 7.1.1.1 says this
already".

SPEC2017 510.parest_r may be one benchmark to evaluate the effect (with
vectorization turned on).

^ permalink raw reply	[flat|nested] 3+ messages in thread

* [Bug target/103568] sub-optimal vector construction with two loaded doubles on Power10
  2021-12-06  2:05 [Bug target/103568] New: sub-optimal vector construction with two loaded doubles on Power10 linkw at gcc dot gnu.org
@ 2021-12-06 11:43 ` segher at gcc dot gnu.org
  2021-12-06 11:43 ` segher at gcc dot gnu.org
  1 sibling, 0 replies; 3+ messages in thread
From: segher at gcc dot gnu.org @ 2021-12-06 11:43 UTC (permalink / raw)
  To: gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103568

--- Comment #1 from Segher Boessenkool <segher at gcc dot gnu.org> ---
Confirmed.

This is cheaper in GPRs until we had the lxvrdx insn, which is power10 (ISA
3.1)
itself.

Wrt dword 1 being zeroed by fp insns.  ISA 3.1 has a note saying this was true
on all earlier implementations (namely, p7, p8, p9) as well.  As far as I know
these are in fact the only older implementations of VSX.

^ permalink raw reply	[flat|nested] 3+ messages in thread

* [Bug target/103568] sub-optimal vector construction with two loaded doubles on Power10
  2021-12-06  2:05 [Bug target/103568] New: sub-optimal vector construction with two loaded doubles on Power10 linkw at gcc dot gnu.org
  2021-12-06 11:43 ` [Bug target/103568] " segher at gcc dot gnu.org
@ 2021-12-06 11:43 ` segher at gcc dot gnu.org
  1 sibling, 0 replies; 3+ messages in thread
From: segher at gcc dot gnu.org @ 2021-12-06 11:43 UTC (permalink / raw)
  To: gcc-bugs

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103568

Segher Boessenkool <segher at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2021-12-06

^ permalink raw reply	[flat|nested] 3+ messages in thread

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2021-12-06 11:43 ` [Bug target/103568] " segher at gcc dot gnu.org
2021-12-06 11:43 ` segher at gcc dot gnu.org

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