From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 9896A3857810; Fri, 21 Jan 2022 18:37:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9896A3857810 From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/103676] [10/11/12 Regression] internal compiler error: in extract_constrain_insn, at recog.c:2671 Date: Fri, 21 Jan 2022 18:37:55 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 11.2.0 X-Bugzilla-Keywords: ice-on-valid-code, inline-asm, ra X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 10.4 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Jan 2022 18:37:56 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103676 --- Comment #24 from CVS Commits --- The master branch has been updated by Vladimir Makarov : https://gcc.gnu.org/g:85419ac59724b7ce710ebb4acf03dbd747edeea3 commit r12-6803-g85419ac59724b7ce710ebb4acf03dbd747edeea3 Author: Vladimir N. Makarov Date: Fri Jan 21 13:34:32 2022 -0500 [PR103676] LRA: Calculate and exclude some start hard registers for rel= oad pseudos LRA and old reload pass uses only one register class for reload pseudos even if operand constraints contain more one register class. Let us consider constraint 'lh' for thumb arm which means low and high thumb registers. Reload pseudo for such constraint will have general reg class (union of low and high reg classes). Assigning the last low register to the relo= ad pseudo is wrong if the pseudo is of DImode as it requires two hard regs. But it is considered OK if we use general reg class. The following pat= ch solves this problem for LRA. gcc/ChangeLog: PR target/103676 * ira.h (struct target_ira): Add member x_ira_exclude_class_mode_regs. (ira_exclude_class_mode_regs): New macro. * lra.h (lra_create_new_reg): Add arg exclude_start_hard_regs a= nd move from here ... * lra-int.h: ... to here. (lra_create_new_reg_with_unique_value): Add arg exclude_start_hard_regs. (class lra_reg): Add member exclude_start_hard_regs. * lra-assigns.cc (find_hard_regno_for_1): Setup impossible_start_hard_regs from exclude_start_hard_regs. * lra-constraints.cc (get_reload_reg): Add arg exclude_start_hard_regs and pass it lra_create_new_reg[_with_unique_value]. (match_reload): Ditto. (check_and_process_move): Pass NULL exclude_start_hard_regs to lra_create_new_reg_with_unique_value. (goal_alt_exclude_start_hard_regs): New static variable. (process_addr_reg, simplify_operand_subreg): Pass NULL exclude_start_hard_regs to lra_create_new_reg_with_unique_value and get_reload_reg. (process_alt_operands): Setup goal_alt_exclude_start_hard_regs. Use this_alternative_exclude_start_hard_regs additionally to fi= nd winning operand alternative. (base_to_reg, base_plus_disp_to_reg, index_part_to_reg): Pass N= ULL exclude_start_hard_regs to lra_create_new_reg. (process_address_1, emit_inc): Ditto. (curr_insn_transform): Pass exclude_start_hard_regs value to lra_create_new_reg, get_reload_reg, match_reload. (inherit_reload_reg, split_reg): Pass NULL exclude_start_hard_r= egs to lra_create_new_reg. (process_invariant_for_inheritance): Ditto. * lra-remat.cc (update_scratch_ops): Ditto. * lra.cc (lra_create_new_reg_with_unique_value): Add arg exclude_start_hard_regs. Setup the corresponding member of lra reg info. (lra_create_new_reg): Add arg exclude_start_hard_regs and pass = it to lra_create_new_reg_with_unique_value. (initialize_lra_reg_info_element): Initialize member exclude_start_hard_regs. (get_scratch_reg): Pass NULL to lra_create_new_reg. * ira.cc (setup_prohibited_class_mode_regs): Rename to setup_prohibited_and_exclude_class_mode_regs and calculate ira_exclude_class_mode_regs. gcc/testsuite/ChangeLog: PR target/103676 * g++.target/arm/pr103676.C: New.=