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From: "vmakarov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/103676] [10/11/12 Regression] internal compiler error:
 in extract_constrain_insn, at recog.c:2671
Date: Mon, 17 Jan 2022 16:43:32 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103676

--- Comment #21 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Jakub Jelinek from comment #19)
> r10-3981-gf6ff841bc8dd87ce364deb217dc6d1ec5dc31de8 still doesn't ICE,
> r10-3984-g22060d0e575e7754eb1355763d22bbe37c3caa13 already ICEs.
>=20
> I guess there is a disagreement between LRA and recog on how exactly they
> treat register constraints.
> "=3Dlh" for TARGET_THUMB means LO_REGS or HI_REGS classes for the output,=
 bet
> LRA sees that LO_REGS or HI_REGS is together GENERAL_REGS and picks a
> GENERAL_REGS
> (reg:DI 7 r7 [orig:119 tmp ] [119]).  But that one has one half in LO_REGS
> and another half in HI_REGS and so extract_constrain_insn ->
> constrain_operands
> doesn't consider it as matching.

Interesting case.  To find required (reload) register class, LRA (as also t=
he
old reload pass) makes some union of register classes in one alternative wh=
ich
contains all or part of the registers of the classes (in this case it is
general reg class).  The problem can be solved w/o fixing LRA (and reload p=
ass)
by using

 asm volatile(
  "ldrd %Q[r], %R[r], %[p]\n"
  : [r]"=3Dl,h"(tmp)
  : [p]"m,m"(*p64)
  : "memory"
 );

The problem can be solved in LRA by more complex representation of required=
 reg
classes (still reload should have also such fix).  I guess it will complica=
te
LRA and reload code a lot.

We could also use more clear description of semantics of constraints curren=
tly
used by LRA/reload.  In this case we still need to output more meaningful e=
rror
for LRA/reload instead of just internal compiler error.=