[Bug target/103722] [12 Regression] ICE in extract_constrain_insn building glibc for SH4

["vmakarov at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103722

--- Comment #1 from Vladimir Makarov <vmakarov at gcc dot gnu.org> ---
(In reply to Joseph S. Myers from comment #0)
> Created attachment 52003 [details]
> preprocessed source
> 
> Build the attached code (from glibc) with -O2 for sh4-linux-gnu.  This
> produces an ICE:
> 
> malloc-debug.c: In function '__debug_realloc':
> malloc-debug.c:267:1: error: insn does not satisfy its constraints:
> (insn 955 1863 2 2 (set (reg:SI 76 fr12 [314])
>         (reg:SI 146 pr)) 189 {movsi_ie}
>      (nil))
> during RTL pass: postreload
> malloc-debug.c:267:1: internal compiler error: in extract_constrain_insn, at
> recog.c:2670
> 0x5eec04 _fatal_insn(char const*, rtx_def const*, char const*, int, char
> const*)
>         /scratch/jmyers/glibc/many12/src/gcc/gcc/rtl-error.c:108
> 0x5eec2a _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
>         /scratch/jmyers/glibc/many12/src/gcc/gcc/rtl-error.c:119
> 0xcab367 extract_constrain_insn(rtx_insn*)
>         /scratch/jmyers/glibc/many12/src/gcc/gcc/recog.c:2670
> 0xc71acd reload_cse_simplify_operands
>         /scratch/jmyers/glibc/many12/src/gcc/gcc/postreload.c:407
> 0xc732bc reload_cse_simplify
>         /scratch/jmyers/glibc/many12/src/gcc/gcc/postreload.c:190
> 0xc732bc reload_cse_regs_1
>         /scratch/jmyers/glibc/many12/src/gcc/gcc/postreload.c:238
> 0xc7584b reload_cse_regs
>         /scratch/jmyers/glibc/many12/src/gcc/gcc/postreload.c:66
> 0xc7584b execute
>         /scratch/jmyers/glibc/many12/src/gcc/gcc/postreload.c:2355
> Please submit a full bug report,
> with preprocessed source if appropriate.
> Please include the complete backtrace with any bug report.
> See <https://gcc.gnu.org/bugs/> for instructions.
> 
> This was introduced (exposed?) by:
> 
> commit a7acb6dca941db2b1c135107dac3a34a20650d5c
> Author: Vladimir N. Makarov <vmakarov@redhat.com>
> Date:   Mon Dec 13 13:48:12 2021 -0500
> 
>     [PR99531] Modify pseudo class cost calculation when processing move
> involving the pseudo and a hard register

I am conforming that it was triggered by my patch.

But it is not an IRA bug.  The old pass reload (used by SH port) fails to
change insn although insn constraints are not satisfied.  The insn in question
is move

fpreg = poreg

The old reload is mistaken by cost of moving prreg to fpreg.  SH machine code
provides cost 2 for this.  In this case the old reload pass skips checking
constraints of the move.

The following patch solves the problem:

diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 0628f059ca2..e7c8e5f84b7 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -10762,6 +10762,12 @@ sh_register_move_cost (machine_mode mode,
       && ! REGCLASS_HAS_GENERAL_REG (dstclass))
     return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);

+  if (((dstclass == FP_REGS || dstclass == DF_REGS)
+       && (srcclass == PR_REGS))
+      || ((srcclass == FP_REGS || srcclass == DF_REGS)
+         && (dstclass == PR_REGS)))
+    return 7;
+
   return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
 }

The patch also makes IRA to allocate a general reg instead of fpreg which is
more costly after applying the patch.