[Bug target/103784] suboptimal code for returning bool value on target ppc

["jskumari at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103784

--- Comment #10 from Surya Kumari Jangala <jskumari at gcc dot gnu.org> ---
After the expand pass, we have a single return bb which first zero extends r117
(this reg holds the return value which has been set by predecessor blocks).
Zero extension is done because r117 is of mode QI and we want to change the
mode to DI. After zero extension, r117 is copied to r3.

The input RTL to the peephole2 pass is similar, ie, the writing of value to r3
occurs in predecessor BBs while zero extension of r3 happens in the return bb.
So we cannot do any peephole optimization to get rid of the unnecessary zero
extension.
Note that when return value is written into r3, it has mode QI. Later in the
return bb, r3 is zero extended to convert it's mode into DI.

However, after the bbro (basic block reordering) pass, we have 2 return BBs.
And in each BB, the return value is copied into r3 (in QI mode), and then r3 is
zero extended. Note that bbro occurs after peephole2.
We can do another peephole after bbro, and get rid of the unnecessary zero
extension.
However, we need not always get an opportunity to do a peephole. That is, the
instructions that write into r3 and zero extend r3 can be in different BBs.

A possible solution to this issue would be to have a separate pass that can
remove the zero extends.

In brief, the new pass can do the following:

Fist create webs.
Then find definitions (that is, writes into registers) that reach zero extend
insns.
Mark such definitions (to indicate that the value is going to be zero extended
later on), and then at the time of assembly generation (final pass),
definitions which have been marked should be converted to assembly instructions
which work on the extended mode (for example, with -m64, the generated assembly
should work on the entire 64bit register instead of just a part of it.).
If we generate such assembly instructions, then the zero extend instruction can
be removed, ie, no assembly need be generated.

Note that for definitions that reach zero extends as well as other uses, we
cannot remove the zero extends.