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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug tree-optimization/103797] Clang vectorized LightPixel while GCC
 does not
Date: Thu, 23 Dec 2021 11:16:31 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103797

--- Comment #17 from Uro=C5=A1 Bizjak <ubizjak at gmail dot com> ---
(In reply to hubicka from comment #16)
> > >=20
> > > It could be done, but I was under impression that the sequence to loa=
d 1.0f
> > > into topmost elements nullifies the benefit of operation to divide two
> >=20
> > Sure, so perhaps we should somewhat increase the vectorization cost of =
V2SFmode
> > division so that we would use it only if it is part of longer sequences?
>=20
> I wonder how the hardware implements it.  If divps is of similar latency
> as divss then I guess it is essentially always win to load 1.0 to the
> upper part, since it is slow operation.  On the other hand if divps is
> about 4 times divss, then this may be harmful.
>=20
> Agner Fog seems to be listing divss and divps with same latencies.
> For zen it is 10 cycles which should be enough to do the setup.

OK, I'll prepare and test a formal patch.=