From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id B5F51385802C; Tue, 11 Jan 2022 18:24:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B5F51385802C From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/103861] [i386] vectorize v2qi vectors Date: Tue, 11 Jan 2022 18:24:10 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 11 Jan 2022 18:24:10 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103861 --- Comment #11 from CVS Commits --- The master branch has been updated by Uros Bizjak : https://gcc.gnu.org/g:820ac79e8448ad6c631e1387ba51a93dcf2b4e89 commit r12-6488-g820ac79e8448ad6c631e1387ba51a93dcf2b4e89 Author: Uros Bizjak Date: Tue Jan 11 19:23:15 2022 +0100 i386: Introduce V2QImode vector cmove for -msse4.1 [PR103861] This patch also moves V2HI and V4QImode vector conditional moves to SSE4.1 targets. Vector cmoves are implemented with SSE logic functi= ons without -msse4.1, and they are hardly worthwile for narrow vector modes. More important, we would like to keep vector logic functions for GPR registers, and the current RTX description of 32-bit vector modes logic insns does not include the necessary CC reg clobber. Solve these issue= s by restricting vector cmove insns for these modes to -msse4.1, where logic instructions are avoided, and pblend insn is used instead. A follow-up patch will add clobbers and necessary splits to 32-bit vector mode logic insns, and in a future patch, ix86_sse_movcc will be improved to use expand_simple_{unop,binop} to emit logic insns, allowing us to re-enable 16-bit and 32-bit narrow vector cmoves for -msse2. 2022-01-11 Uro=C3=85=C2=A1 Bizjak gcc/ChangeLog: PR target/103861 * config/i386/mmx.md (vcond): Use VI_16_32 mode iterator. Enable for TARGET_SSE4_1. (vcondu): Ditto. (vcond_mask_): Ditto. (mmx_pblendvb_v8qi): Rename from mmx_pblendvb64. (mmx_pblendvb_): Rename from mmx_pblendvb32. Use VI_16_32 mode iterator. * config/i386/i386-expand.c (ix86_expand_sse_movcc): Update for rename. Handle V2QImode. (expand_vec_perm_blend): Update for rename. gcc/testsuite/ChangeLog: PR target/103861 * g++.target/i386/pr100637-1b.C (dg-options): Use -msse4 instead of -msse2. * g++.target/i386/pr100637-1w.C (dg-options): Ditto. * g++.target/i386/pr103861-1.C: New test. * gcc.target/i386/pr100637-4b.c (dg-options): Use -msse4 instead of -msse2. * gcc.target/i386/pr103861-4.c: New test.=