From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id E0FB53858D28; Thu, 30 Dec 2021 22:03:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E0FB53858D28 From: "petro.karashchenko at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug middle-end/103870] New: ARM: Wrong branch instruction with optimization O2 and higher Date: Thu, 30 Dec 2021 22:03:06 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: middle-end X-Bugzilla-Version: 10.3.1 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: petro.karashchenko at gmail dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Dec 2021 22:03:07 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D103870 Bug ID: 103870 Summary: ARM: Wrong branch instruction with optimization O2 and higher Product: gcc Version: 10.3.1 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: petro.karashchenko at gmail dot com Target Milestone: --- Code test.c: void f(void) { double a =3D 2.2204460492503131e-16; int b =3D 1; int c =3D 0; while (a > 0) { if (++c >=3D 10) { b *=3D 2; c =3D 0; } if (b > 1) { a *=3D b; } } } ---------- arm-none-eabi-gcc -save-temps -Wall -Wextra -c -march=3Darmv7e-m -mtune=3Dc= ortex-m7 -mthumb -mfpu=3Dfpv5-d16 -mfloat-abi=3Dhard test.c -O0 ---------- Generated assembly: .arch armv7e-m .fpu fpv5-d16 .eabi_attribute 28, 1 .eabi_attribute 20, 1 .eabi_attribute 21, 1 .eabi_attribute 23, 3 .eabi_attribute 24, 1 .eabi_attribute 25, 1 .eabi_attribute 26, 1 .eabi_attribute 30, 6 .eabi_attribute 34, 1 .eabi_attribute 18, 4 .file "test2.c" .text .align 1 .global f .syntax unified .thumb .thumb_func .type f, %function f: @ args =3D 0, pretend =3D 0, frame =3D 16 @ frame_needed =3D 1, uses_anonymous_args =3D 0 @ link register save eliminated. push {r7} sub sp, sp, #20 add r7, sp, #0 mov r2, #0 ldr r3, .L5 strd r2, [r7, #8] movs r3, #1 str r3, [r7, #4] movs r3, #0 str r3, [r7] b .L2 .L4: ldr r3, [r7] adds r3, r3, #1 str r3, [r7] ldr r3, [r7] cmp r3, #9 ble .L3 ldr r3, [r7, #4] lsls r3, r3, #1 str r3, [r7, #4] movs r3, #0 str r3, [r7] .L3: ldr r3, [r7, #4] cmp r3, #1 ble .L2 ldr r3, [r7, #4] vmov s15, r3 @ int vcvt.f64.s32 d7, s15 vldr.64 d6, [r7, #8] vmul.f64 d7, d6, d7 vstr.64 d7, [r7, #8] .L2: vldr.64 d7, [r7, #8] vcmpe.f64 d7, #0 vmrs APSR_nzcv, FPSCR bgt .L4 nop nop adds r7, r7, #20 mov sp, r7 @ sp needed ldr r7, [sp], #4 bx lr .L6: .align 2 .L5: .word 1018167296 .size f, .-f .ident "GCC: (GNU Arm Embedded Toolchain 10.3-2021.10) 10.3.1 2021= 0824 (release)" ---------- arm-none-eabi-gcc -save-temps -Wall -Wextra -c -march=3Darmv7e-m -mtune=3Dc= ortex-m7 -mthumb -mfpu=3Dfpv5-d16 -mfloat-abi=3Dhard test.c -Os ---------- Generated assembly: .arch armv7e-m .fpu fpv5-d16 .eabi_attribute 28, 1 .eabi_attribute 20, 1 .eabi_attribute 21, 1 .eabi_attribute 23, 3 .eabi_attribute 24, 1 .eabi_attribute 25, 1 .eabi_attribute 26, 1 .eabi_attribute 30, 4 .eabi_attribute 34, 1 .eabi_attribute 18, 4 .file "test2.c" .text .align 1 .global f .syntax unified .thumb .thumb_func .type f, %function f: @ args =3D 0, pretend =3D 0, frame =3D 0 @ frame_needed =3D 0, uses_anonymous_args =3D 0 @ link register save eliminated. vldr.64 d7, .L10 movs r3, #0 movs r2, #1 .L5: adds r3, r3, #1 cmp r3, #9 ble .L2 lsls r2, r2, #1 movs r3, #0 .L3: vmov s13, r2 @ int vcvt.f64.s32 d6, s13 vmul.f64 d7, d7, d6 b .L4 .L2: cmp r2, #1 bne .L3 .L4: vcmpe.f64 d7, #0 vmrs APSR_nzcv, FPSCR bgt .L5 bx lr .L11: .align 3 .L10: .word 0 .word 1018167296 .size f, .-f .ident "GCC: (GNU Arm Embedded Toolchain 10.3-2021.10) 10.3.1 2021= 0824 (release)" ---------- The problem appears with condition "if (b > 1)". If -O0 is applied then code ldr r3, [r7, #4] cmp r3, #1 ble .L2 is generate that "ble" instruction code is used, however with -Os we are getting cmp r2, #1 bne .L3 code generated that use "bne" instruction code. The case is that with code above "b *=3D 2;" at some point "b" overflows and becomes equal to zero. The "ble" instruction code will catch this however "bne" will not. So usage of "bne" is inappropriate for "if (b > 1)" condition that is intended to trunc= ate negative values and zero.=