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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/103926] "wQ" broken Date: Thu, 06 Jan 2022 02:26:12 +0000 [thread overview] Message-ID: <bug-103926-4-aEOX3CzyYU@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-103926-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103926 Andrew Pinski <pinskia at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Keywords|ice-on-valid-code |ice-on-invalid-code --- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> --- The constraint is not documented even because it looks like an internal only one: ;; Lq/stq validates the address for load/store quad (define_memory_constraint "wQ" "@internal Memory operand suitable for the load/store quad instructions." (match_operand 0 "quad_memory_operand")) Note your inline-asm is broken but GCC should not be crashing. I think the following will work: __int128 f(void *ptr) { __int128 v; asm volatile("lq %0, 0(%1)" : "=&r" (v) : "wQ" (*(__int128 *)ptr)); return v; } But there still some other stuff that you need to do. The constraint is failing because you don't have a memory passed to the inline-asm only the register and it is the wrong size, it is a 64bit rather than 128bit.
next prev parent reply other threads:[~2022-01-06 2:26 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-06 2:10 [Bug other/103926] New: " aik at ozlabs dot ru 2022-01-06 2:12 ` [Bug target/103926] " pinskia at gcc dot gnu.org 2022-01-06 2:26 ` pinskia at gcc dot gnu.org [this message] 2022-01-06 3:43 ` aik at ozlabs dot ru 2022-01-06 3:50 ` pinskia at gcc dot gnu.org 2022-02-23 14:43 ` segher at gcc dot gnu.org
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