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From: "gjl at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/103975] DWARF .debug_frame incorrect for ISRs on AVR; pushing SREG creates off-by-one error
Date: Wed, 26 Oct 2022 20:35:20 +0000	[thread overview]
Message-ID: <bug-103975-4-IExqmak8qs@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-103975-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103975

--- Comment #5 from Georg-Johann Lay <gjl at gcc dot gnu.org> ---
If someone is going to fix this, the following changes might also play a role:

* v8+ may emit optimized ISR prologues / epilogues using PR81268: gcc will just
emit pseudo-instruction __gcc_isr which will be resolved by gas.  Debug info
might be incorrect or missing; gas would have to add respective debug info.

* v12+ PR92729 changed condition code from implicit cc0 to explicit REG_CC and
introduced a new hard register "cc" with hard register number REG_CC = 36. The
highest hard regno before that transition was 35.

      parent reply	other threads:[~2022-10-26 20:35 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-11  7:53 [Bug debug/103975] New: " kimballa at apache dot org
2022-01-11  7:54 ` [Bug debug/103975] " kimballa at apache dot org
2022-01-11  8:09 ` pinskia at gcc dot gnu.org
2022-01-11  9:15 ` [Bug target/103975] " kimballa at apache dot org
2022-01-11  9:16 ` kimballa at apache dot org
2022-10-26 20:35 ` gjl at gcc dot gnu.org [this message]

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