[Bug target/104039] New: AArch64 Redundant instruction moving general to vector register

["nate at thatsmathematics dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104039

            Bug ID: 104039
           Summary: AArch64 Redundant instruction moving general to vector
                    register
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: nate at thatsmathematics dot com
  Target Milestone: ---

Compiling the following code on AArch64 with -O2 or -O3:

typedef unsigned long u64x2 __attribute__((vector_size(16)));

u64x2 combine(unsigned long a, unsigned long b) {
        u64x2 v = {a,b};
    return v;
}

yields the following assembly:

combine:
        fmov    d0, x0
        ins     v0.d[1], x1
        ins     v0.d[1], x1
        ret

where the second ins is entirely redundant with the first and serves no
apparent purpose.  (Unless it is something extremely clever...)

This seems to be a regression from 8.x to 9.x; Godbolt's 8.5 looks correct with
just one ins, but 9.3 has the two.

Originally noticed by Peter Cordes on StackOverflow:
https://stackoverflow.com/questions/70717360/how-to-load-vector-registers-from-integer-registers-in-arm64-m1/70718572#comment125016906_70717360