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From: "roger at nextmovesoftware dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/104345] nvptx: "regression" after "nvptx: Transition nvptx backend to STORE_FLAG_VALUE = 1" Date: Wed, 02 Feb 2022 14:26:59 +0000 [thread overview] Message-ID: <bug-104345-4-0nx4da9hJv@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-104345-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104345 Roger Sayle <roger at nextmovesoftware dot com> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |roger at nextmovesoftware dot com Status|UNCONFIRMED |NEW Last reconfirmed| |2022-02-02 Ever confirmed|0 |1 --- Comment #1 from Roger Sayle <roger at nextmovesoftware dot com> --- Hi Torsten, Thanks for the bug report. The STORE_FLAG_VALUE=1 patch was one of a series to dramatically improve the quality of nvptx code. Alas not all of them have yet been reviewed/approved, and it's likely these later improvements address the quality regression you're seeing. The other patches in the "nvptx Boolean" series are: patchq3: nvptx: Expand QI mode operations using SI mode instructions. https://gcc.gnu.org/pipermail/gcc-patches/2022-January/587999.html patchq4: nvptx: Fix and use BI mode logic instructions (e.g. and.pred). https://gcc.gnu.org/pipermail/gcc-patches/2022-January/588555.html [and purely for reference, my other outstanding nvptx patches are] patchn: nvptx: Improved support for HFMode including neghf2 and abshf2. https://gcc.gnu.org/pipermail/gcc-patches/2022-January/587949.html patchw: nvptx: Add support for 64-bit mul.hi (and other) instructions. https://gcc.gnu.org/pipermail/gcc-patches/2022-January/588453.html And one other related patch is that there's also a middle-end SUBREG patch intended to improve code generation on nvptx is also pending at: patchs: Simplify paradoxical subreg extensions of TRUNCATE https://gcc.gnu.org/pipermail/gcc-patches/2021-September/578848.html My guess is that patchq3+patchq4 above should (hopefully) resolve this particular regression. If you could give them a spin on your system to see if they reduce register pressure sufficiently for this case, that would be greatly appreciated. As you can read in the above postings, the total number of instructions/registers (after all of these changes) should be dramatically reduced. I'll see what I can do from my end.
next prev parent reply other threads:[~2022-02-02 14:26 UTC|newest] Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-02-02 14:10 [Bug target/104345] New: " tschwinge at gcc dot gnu.org 2022-02-02 14:26 ` roger at nextmovesoftware dot com [this message] 2022-02-02 22:37 ` [Bug target/104345] [12 Regression] "nvptx: Transition nvptx backend to STORE_FLAG_VALUE = 1" patch made some code generation worse pinskia at gcc dot gnu.org 2022-02-03 14:17 ` vries at gcc dot gnu.org 2022-02-03 21:09 ` roger at nextmovesoftware dot com 2022-02-08 11:53 ` tschwinge at gcc dot gnu.org 2022-02-08 11:54 ` tschwinge at gcc dot gnu.org 2022-02-08 11:55 ` tschwinge at gcc dot gnu.org 2022-02-08 11:57 ` tschwinge at gcc dot gnu.org 2022-02-08 12:33 ` tschwinge at gcc dot gnu.org 2022-02-08 15:36 ` tschwinge at gcc dot gnu.org 2022-02-10 8:02 ` cvs-commit at gcc dot gnu.org 2022-02-10 8:02 ` cvs-commit at gcc dot gnu.org 2022-03-02 12:10 ` roger at nextmovesoftware dot com
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