From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 74F283858D1E; Thu, 28 Apr 2022 07:09:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 74F283858D1E From: "crazylht at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/104375] [x86] Failure to recognize bzhi pattern when shr is present Date: Thu, 28 Apr 2022 07:09:38 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: enhancement X-Bugzilla-Who: crazylht at gmail dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Apr 2022 07:09:38 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104375 --- Comment #1 from Hongtao.liu --- backend has=20 16550(define_insn "*bmi2_bzhi_3_2" 16551 [(set (match_operand:SWI48 0 "register_operand" "=3Dr") 16552 (and:SWI48 16553 (plus:SWI48 16554 (ashift:SWI48 (const_int 1) 16555 (match_operand:QI 2 "register_operand" "r")) 16556 (const_int -1)) 16557 (match_operand:SWI48 1 "nonimmediate_operand" "rm"))) 16558 (clobber (reg:CC FLAGS_REG))] 16559 "TARGET_BMI2" 16560 "bzhi\t{%2, %1, %0|%0, %1, %2}" 16561 [(set_attr "type" "bitmanip") 16562 (set_attr "prefix" "vex") 16563 (set_attr "mode" "")]) But there's extra zero_extend in pattern match. 315Failed to match this instruction: 316(parallel [ 317 (set (reg:DI 90) 318 (zero_extend:DI (and:SI (plus:SI (reg:SI 91) 319 (const_int -1 [0xffffffffffffffff])) 320 (subreg:SI (reg:DI 95) 0)))) 321 (clobber (reg:CC 17 flags)) 322 ])=