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From: "ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/104458] [11/12 Regression] ICE: SIGSEGV in
 gen_udivmodhiqi3 -> copy_rtx with -O1 -m8bit-idiv
Date: Wed, 09 Feb 2022 10:54:56 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104458

Uro=C5=A1 Bizjak <ubizjak at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
           Assignee|unassigned at gcc dot gnu.org      |ubizjak at gmail do=
t com
   Last reconfirmed|                            |2022-02-09
     Ever confirmed|0                           |1

--- Comment #1 from Uro=C5=A1 Bizjak <ubizjak at gmail dot com> ---
The testcase is quite creative with casts, creating:

(gdb) p debug_rtx ( operands[3])
(subreg:DI (reg:V2SF 96) 0)

which chokes lowpart_subreg. So, force inputs to a register, which is
preferable even when the input is from a memory.

--cut here--
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index eb1930ba375..ce9607e36de 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -1407,6 +1407,9 @@ ix86_split_idivmod (machine_mode mode, rtx operands[],
   rtx scratch, tmp0, tmp1, tmp2;
   rtx (*gen_divmod4_1) (rtx, rtx, rtx, rtx);

+  operands[2] =3D force_reg (mode, operands[2]);
+  operands[3] =3D force_reg (mode, operands[3]);
+
   switch (mode)
     {
     case E_SImode:
--cut here--=