[Bug target/104590] New: ppc64: even/odd permutation for VSX 64-bit to 32-bit conversions is no longer necessary.

["seiko at imavr dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104590

            Bug ID: 104590
           Summary: ppc64: even/odd permutation for VSX 64-bit to 32-bit
                    conversions is no longer necessary.
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: seiko at imavr dot com
  Target Milestone: ---

Created attachment 52473
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=52473&action=edit
proposal patch remove the extra shuffles

The following VSX intrinsics did not need to exist in the first place, and they
must be replaced or renamed by convinced names suitable to the mapped
instructions or at least modified by removing the unnecessary shuffles:

- vector unsigned int vec_unsignede(vector double) -> xvcvdpuxws
- vector unsigned int vec_unsignedo(vector double) -> xvcvdpuxws
- vector float vec_floate(vector double) -> xvcvdpsp
- vector float vec_floato(vector double) -> xvcvdpsp
- vector float vec_floate(vector signed long long) -> xvcvsxdsp
- vector float vec_floato(vector signed long long) -> xvcvsxdsp
- vector float vec_floate(vector unsigned long long) -> xvcvuxdsp
- vector float vec_floato(vector unsigned long long) -> xvcvuxdsp

According to the latest update of ISA 3.1:

Previous versions of the architecture allowed the contents of bits 32:63 of
each doubleword in the result register to be undefined, however, all processors
that support this instruction write the result into bits 32:63 of each
doubleword in the result register
as well as into bits 0:31, as is required by this version of the architecture.