From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 8DBDE3858D28; Wed, 23 Feb 2022 22:17:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8DBDE3858D28 From: "christophm30 at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/104657] array subscript 0 is outside array bounds Date: Wed, 23 Feb 2022 22:17:58 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: christophm30 at gmail dot com X-Bugzilla-Status: RESOLVED X-Bugzilla-Resolution: DUPLICATE X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Feb 2022 22:17:58 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104657 --- Comment #4 from Christoph M=C3=BCllner = --- Thanks for mentioning the volatile pointer method. However, the pragma-solution results in better code (fewer instructions and does not require a valid stack pointer). I've used the code below to see what happens on AArch64 and RISC-V 64-bit: #define MEM_ADDR 0xffff8000 void foo_warning(unsigned long v) { volatile unsigned long * p; p =3D (void*)MEM_ADDR; *p =3D v; } void foo_warningfree(unsigned long v) { volatile unsigned long * p; p =3D (void*)MEM_ADDR; #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Warray-bounds" *p =3D v; #pragma GCC diagnostic pop } void foo_volatile(unsigned long v) { volatile unsigned long * volatile p; p =3D (void*)MEM_ADDR; *p =3D v; } AArch64: foo_warning: mov x1, 4294934528 str x0, [x1] ret foo_warningfree: mov x1, 4294934528 str x0, [x1] ret foo_volatile: sub sp, sp, #16 mov x1, 4294934528 str x1, [sp, 8] ldr x1, [sp, 8] str x0, [x1] add sp, sp, 16 ret RISC-V 64-bit: foo_warning: li a5,536866816 slli a5,a5,3 sd a0,0(a5) ret foo_warningfree: li a5,536866816 slli a5,a5,3 sd a0,0(a5) ret foo_volatile: li a5,536866816 addi sp,sp,-16 slli a5,a5,3 sd a5,8(sp) ld a5,8(sp) sd a0,0(a5) addi sp,sp,16 jr ra=