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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/104683] -march=haswell generates invalid instructions on Celeron Haswell CPUs
Date: Fri, 25 Feb 2022 10:38:39 +0000	[thread overview]
Message-ID: <bug-104683-4-ZIVlbKN0So@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-104683-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104683

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |INVALID
             Status|WAITING                     |RESOLVED

--- Comment #3 from Richard Biener <rguenth at gcc dot gnu.org> ---
G5905 aka Comet Lake also has no AVX (but that's just skylake++ and we don't
have any -march= for those).

Note that our documentation says:

@item haswell
Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDRND,
F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE and HLE instruction set support.

so it explicitely mentions AVX2 - that means you cannot match Intel Product
Names and GCC -march= identifiers 1:1.  So I'd say it works as intended.

  parent reply	other threads:[~2022-02-25 10:38 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-25  2:22 [Bug other/104683] New: " pc-gcc22 at crowcastle dot net
2022-02-25  8:27 ` [Bug target/104683] " rguenth at gcc dot gnu.org
2022-02-25 10:32 ` rguenth at gcc dot gnu.org
2022-02-25 10:38 ` rguenth at gcc dot gnu.org [this message]
2022-02-25 14:37 ` pc-gcc22 at crowcastle dot net

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