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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/104683] -march=haswell generates invalid instructions on
 Celeron Haswell CPUs
Date: Fri, 25 Feb 2022 10:38:39 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104683

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |INVALID
             Status|WAITING                     |RESOLVED

--- Comment #3 from Richard Biener <rguenth at gcc dot gnu.org> ---
G5905 aka Comet Lake also has no AVX (but that's just skylake++ and we don't
have any -march=3D for those).

Note that our documentation says:

@item haswell
Intel Haswell CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE=
3,
SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE, RDR=
ND,
F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE and HLE instruction set support.

so it explicitely mentions AVX2 - that means you cannot match Intel Product
Names and GCC -march=3D identifiers 1:1.  So I'd say it works as intended.=