From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id DCCAC385B187; Mon, 28 Nov 2022 20:11:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DCCAC385B187 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669666280; bh=xLhcs9p5o755u1vjwCvwdeS8LeYry4Sd5Q1TIHVz2Cs=; h=From:To:Subject:Date:In-Reply-To:References:From; b=iikhuFN9UW/eZWiUPzURq63c4vDSh51XNdQv1p25SmCkprHvaTeTMJtyNsniKSBo4 Qnf/xuLMzkHTxJmbJoquOrVib/a3WlfcmZvjx5ZoxJEyC2Uics+5wN6KCHIdxK4MxH lfX/TxPelSHHOrCKT2RXHYsscSZiuGIn8yP7GAfA= From: "amonakov at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/104688] gcc and libatomic can use SSE for 128-bit atomic loads on Intel and AMD CPUs with AVX Date: Mon, 28 Nov 2022 20:11:20 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: missed-optimization, patch X-Bugzilla-Severity: normal X-Bugzilla-Who: amonakov at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104688 --- Comment #26 from Alexander Monakov --- Sure, the right course of action seems to be to simply document that atomic types and built-ins are meant to be used on "common" (writeback) memory, an= d no guarantees can be given otherwise, because it would involve platform specif= ics (relaxed ordering of WC writes as you say; tearing by PCI bridges and device interfaces seems like another possible caveat).=