From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id AD59B3858412; Mon, 14 Nov 2022 09:29:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AD59B3858412 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668418171; bh=c0XihspSkVDCiYFlDJQoHPiSytjRWXScVAwaOsJkFCo=; h=From:To:Subject:Date:In-Reply-To:References:From; b=bpgylHwiupW3DB2U/HxMnHUGhPVvQ9sZWy9qTAPam4c9VUn+rcIc+vXasDWwQKoLL fuw3NatMnz6qKny0aVtuTOuLgfF2VDFMafv1tTBK3eagaRFw1qPT+MONF34RFfqRud wEai3tL1LQ7GKtW+5g/MlzAOokjDXQj/QzH27nzU= From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/104688] gcc and libatomic can use SSE for 128-bit atomic loads on Intel and AMD CPUs with AVX Date: Mon, 14 Nov 2022 09:29:30 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: missed-optimization, patch X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104688 --- Comment #14 from Jakub Jelinek --- For ordering guarantees I assume (already since the r12-7689 change) that VMOVDQA behaves the same as MOVL/MOVQ. This PR was about whether there is a quarantee that VMOVDQA will be an atom= ic load or store provided 128-bit aligned address.=