From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 3773B385457E; Wed, 23 Nov 2022 09:51:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3773B385457E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669197106; bh=yjhdkvXRPAYQuNBJSXMAqlbjYg/DtF2UpTcsqloo9io=; h=From:To:Subject:Date:In-Reply-To:References:From; b=jsfYDA1+LzNmj8859EX1eVilp3jc2BYv0Kw3gH9QUAhiUKoIsa9vQp4y2FVe0VosZ Nj0cUcWXrkEn54Fwe/GviF5duCHeswZNfyc7fnoLpKfJwbQEevKzFENRyqvffXPJuf 5Vl4kRCWOnnDWPbx4Fru9XSKeLDs0AjcBEFCJJLw= From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/104688] gcc and libatomic can use SSE for 128-bit atomic loads on Intel and AMD CPUs with AVX Date: Wed, 23 Nov 2022 09:51:44 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: missed-optimization, patch X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104688 --- Comment #21 from Jakub Jelinek --- What about loads? That is even more important than the stores. While atom= ic store can be worst case done through cmpxchg16b, even when it is slower, we can't use cmpxchg16b on atomic load because we don't know if the memory isn= 't read-only. As for the Write Back only vs. other types, doesn't that match the " for cacheable" in the AMD statement?=