From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id EAE48385B526; Mon, 28 Nov 2022 19:03:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EAE48385B526 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669662188; bh=vPrRmfN/MbRskDjhpsFQ2/5Wz4vr4lrrztK9DCQVXcU=; h=From:To:Subject:Date:In-Reply-To:References:From; b=UEjfYj3l/u35frj5qFppC5UnS7XSn29wEhDXLhhhNCTJjoUbgH4MJ1AY+u7uom2LC s0Yzqvro/HfPGzjsxdHNnXcoD2yP2Ftknre9gIEYmFI6CcMXB7ui3OAHizU2bAYBdF LG8DvKYyWEgfTYjLalMii3+OBtNutxuGufHzDFDY= From: "peter at cordes dot ca" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/104688] gcc and libatomic can use SSE for 128-bit atomic loads on Intel and AMD CPUs with AVX Date: Mon, 28 Nov 2022 19:03:07 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: missed-optimization, patch X-Bugzilla-Severity: normal X-Bugzilla-Who: peter at cordes dot ca X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104688 --- Comment #25 from Peter Cordes --- (In reply to Alexander Monakov from comment #24) >=20 > I think it's possible to get UC/WC mappings via a graphics/compute API (e= .g. > OpenGL, Vulkan, OpenCL, CUDA) on any OS if you get a mapping to device > memory (and then CPU vendor cannot guarantee that 128b access won't tear > because it might depend on downstream devices). Even atomic_int doesn't work properly if you deref a pointer to WC memory. = WC doesn't have the same ordering guarantees, so it would break acquire/release semantics. So we already don't support WC for this. We do at least de-facto support atomics on UC memory because the ordering guarantees are a superset of cacheable memory, and 8-byte atomicity for ali= gned load/store is guaranteed even for non-cacheable memory types since P5 Penti= um (and on AMD). (And lock cmpxchg16b is always atomic even on UC memory.) But you're right that only Intel guarantees that 16-byte VMOVDQA loads/stor= es would be atomic on UC memory. So this change could break that very unwise corner-case on AMD which only guarantees that for cacheable loads/stores, a= nd Zhaoxin only for WB. But was anyone previously using 16-byte atomics on UC device memory? Do we actually care about supporting that? I'd guess no and no, so it's just a matter of documenting that somewhere. Since GCC7 we've reported 16-byte atomics as being non-lock-free, so I *hop= e* people weren't using __atomic_store_n on device memory. The underlying implementation was never guaranteed.=