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From: "fw at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/104688] gcc and libatomic can use SSE for 128-bit atomic
 loads on Intel and AMD CPUs with AVX
Date: Wed, 15 Feb 2023 12:46:56 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104688

--- Comment #30 from Florian Weimer <fw at gcc dot gnu.org> ---
(In reply to Segher Boessenkool from comment #29)
> (In reply to Florian Weimer from comment #28)
> > Maybe this belongs in the ABI manual? For example, the POWER ABI says t=
hat
> > memcpy needs to work on device memory.
>=20
> Huh?!
>=20
> Where do you see this?  The way you state it it is trivially impossible to
> implement, so if we really say that it needs fixing asap.

I thought I had an explicit documented reference somewhere, but for now, al=
l we
have is an undocumented requirement (so not a good example in the context of
this bug at all):

[PATCH] powerpc: Use aligned stores in memset
<https://inbox.sourceware.org/libc-alpha/1503033107-20047-1-git-send-email-=
raji@linux.vnet.ibm.com/>

(There's also a CPU quirk in this area, but I think this wasn't about that.=
)=