From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-bugzilla@gcc.gnu.org>
Received: by sourceware.org (Postfix, from userid 48)
	id 7FFC03852C4D; Wed, 23 Nov 2022 10:23:04 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7FFC03852C4D
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1669198984;
	bh=ISdDfY289any779cmAwTZ5EFHHqAlcb3CHmsMVZZLAY=;
	h=From:To:Subject:Date:In-Reply-To:References:From;
	b=EJcc6MaAHsBXeFgHs84GwhA/2XYSpefZXMERxbqaQiGxin6M7qOLmKzYPBfrxytKt
	 e0mU4KOGtX6LLYKSCVAi8h1Ija3M5E5U/Zxaiw0NN0Y1WG1mhbDE4RB26cYdg/r1vZ
	 wEsROuHRJEHdgIN+RUkrtgmuWeDf0PtGHhlLA2bk=
From: "xry111 at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/104688] gcc and libatomic can use SSE for 128-bit atomic
 loads on Intel and AMD CPUs with AVX
Date: Wed, 23 Nov 2022 10:23:03 +0000
X-Bugzilla-Reason: CC
X-Bugzilla-Type: changed
X-Bugzilla-Watch-Reason: None
X-Bugzilla-Product: gcc
X-Bugzilla-Component: target
X-Bugzilla-Version: 12.0
X-Bugzilla-Keywords: missed-optimization, patch
X-Bugzilla-Severity: normal
X-Bugzilla-Who: xry111 at gcc dot gnu.org
X-Bugzilla-Status: NEW
X-Bugzilla-Resolution: 
X-Bugzilla-Priority: P3
X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org
X-Bugzilla-Target-Milestone: ---
X-Bugzilla-Flags: 
X-Bugzilla-Changed-Fields: 
Message-ID: <bug-104688-4-bQKrLcaEEC@http.gcc.gnu.org/bugzilla/>
In-Reply-To: <bug-104688-4@http.gcc.gnu.org/bugzilla/>
References: <bug-104688-4@http.gcc.gnu.org/bugzilla/>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/
Auto-Submitted: auto-generated
MIME-Version: 1.0
List-Id: <gcc-bugs.sourceware.org>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104688

--- Comment #22 from Xi Ruoyao <xry111 at gcc dot gnu.org> ---
(In reply to Jakub Jelinek from comment #21)
> What about loads?  That is even more important than the stores.  While
> atomic store can be worst case done through cmpxchg16b, even when it is
> slower, we can't use cmpxchg16b on atomic load because we don't know if t=
he
> memory isn't read-only.

Loads are also atomic for WB.

> As for the Write Back only vs. other types, doesn't that match the
> " for cacheable" in the AMD statement?

If I read the manual correctly, Write Back, Write Through, and Write Protec=
ted
are all "cacheable".  Mayshao told me VMOVDQA is atomic for WB, but not ato=
mic
for UC and WC (they are not cacheable so I think we don't need to take care=
).=20
So how about WT and WP?=