From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 192B73858D28; Sat, 26 Feb 2022 03:58:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 192B73858D28 From: "meissner at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/104698] New: Inefficient code for DI to TI sign extend on power10 Date: Sat, 26 Feb 2022 03:58:43 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 11.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: meissner at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status bug_severity priority component assigned_to reporter target_milestone Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 26 Feb 2022 03:58:44 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104698 Bug ID: 104698 Summary: Inefficient code for DI to TI sign extend on power10 Product: gcc Version: 11.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: meissner at gcc dot gnu.org Target Milestone: --- On power10, signed conversion from DImode to TImode is inefficient for GCC = 11 and the current GCC 12. GCC 10 does not do this optimization. On power10, GCC tries to generate the 'vextsd2q' instruction. However, to generate this instruction, it would typically generate a 'mtvsrsdd' instruc= tion to get the TImode value into an Altivec register in the bottom 64-bits, the= n it does the vextsd2g instruction, and finally it generates 'mfvsrd' and 'mfvsr= ld' instructions to get the value back into the GPR registers. For power9, it generates a move instruction and then an arithmetic shift ri= ght 63 bits to fill the upper word with the copy of the sign bit. GCC should generate the following code sequences: 1) For GPR register to GPR register: Move register, and 'sradi' to create t= he sign bits in the upper word. 2) For GPR register to VSX register to Altivec register: Splat the value to fill the bottom 64 bits, and then do 'vextsd2q'. 3) For memory to GPR register, load the value into the low register, and fi= ll the high register with the sign bit. 4) For memory to Altivec register, load the value with load VSX vector rightmost doubleword, and then do 'vextsd2q'.=