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Subject: [Bug target/104790] [12 Regression] ICE (insn does not satisfy its
 constraints) with MVE since
 r12-4374-g5efeaa0d29525fa28e189e6278c1b1651fb0d7bf
Date: Tue, 08 Mar 2022 17:51:12 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104790

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Andre Simoes Dias Vieira
<avieira@gcc.gnu.org>:

https://gcc.gnu.org/g:796f5220c808bc37adbd1081476589ab1a5d7ac3

commit r12-7538-g796f5220c808bc37adbd1081476589ab1a5d7ac3
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Tue Mar 8 17:46:40 2022 +0000

    arm: MVE: Relax addressing modes for full loads and stores

    This patch relaxes the addressing modes for the mve full load and stores
(by
    full loads and stores I mean non-widening or narrowing loads and stores
resp).
    The code before was requiring a LO_REGNUM for these, where this is only=
 a
    requirement if the load is widening or the store narrowing.

    gcc/ChangeLog:

            PR target/104790
            * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO.
            * config/arm/arm.cc (mve_vector_mem_operand): Relax constraint =
on
base
            register for non widening loads or narrowing stores.=