[Bug target/104790] New: [12 Regression] ICE (insn does not satisfy its constraints) with MVE since r12-4374-g5efeaa0d29525fa28e189e6278c1b1651fb0d7bf

[Bug target/104790] New: [12 Regression] ICE (insn does not satisfy its constraints) with MVE since r12-4374-g5efeaa0d29525fa28e189e6278c1b1651fb0d7bf

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104790

            Bug ID: 104790
           Summary: [12 Regression] ICE (insn does not satisfy its
                    constraints) with MVE since
                    r12-4374-g5efeaa0d29525fa28e189e6278c1b1651fb0d7bf
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: acoplan at gcc dot gnu.org
  Target Milestone: ---

The following ICE was reduced from the testsuite:

$ cat t.c
typedef short V __attribute__((vector_size(16)));
V b, c, d;
void f() {
  int i;
  c = d;
  i = 0;
  for (; i < 8; ++i)
    if (d[i & -i] != b[d[i] - 1])
      __builtin_abort();
}
$ gcc/xgcc -B gcc -c t.c -march=armv8.1-m.main+mve -mfloat-abi=hard -O
t.c: In function ‘f’:
t.c:10:1: error: insn does not satisfy its constraints:
   10 | }
      | ^
(insn 12 78 3 2 (set (mem/c:V8HI (post_modify:SI (reg:SI 12 ip [orig:122
ivtmp.10 ] [122])
                (plus:SI (reg:SI 12 ip [orig:122 ivtmp.10 ] [122])
                    (const_int 14 [0xe]))) [1 c+0 S16 A64])
        (reg:V8HI 28 s12 [152])) "t.c":5:5 3029 {*mve_movv8hi}
     (expr_list:REG_INC (reg:SI 12 ip [orig:122 ivtmp.10 ] [122])
        (nil)))
during RTL pass: reload
t.c:10:1: internal compiler error: in extract_constrain_insn, at recog.cc:2670
0x60d898 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /home/alecop01/toolchain/src/gcc/gcc/rtl-error.cc:108
0x60d8c1 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /home/alecop01/toolchain/src/gcc/gcc/rtl-error.cc:118
0xcefe5d extract_constrain_insn(rtx_insn*)
        /home/alecop01/toolchain/src/gcc/gcc/recog.cc:2670
0xbaea17 check_rtl
        /home/alecop01/toolchain/src/gcc/gcc/lra.cc:2095
0xbb3f1d lra(_IO_FILE*)
        /home/alecop01/toolchain/src/gcc/gcc/lra.cc:2513
0xb60779 do_reload
        /home/alecop01/toolchain/src/gcc/gcc/ira.cc:5940
0xb60779 execute
        /home/alecop01/toolchain/src/gcc/gcc/ira.cc:6126
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.

It seems to have started with:

commit 5efeaa0d29525fa28e189e6278c1b1651fb0d7bf
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Wed Oct 13 16:42:47 2021

    [arm] Fix MVE addressing modes for VLDR[BHW] and VSTR[BHW]

I can see the following ICEs in the testsuite:

FAIL: c-c++-common/torture/vshuf-v8hi.c   -Os  (internal compiler error: in
extract_constrain_insn, at recog.cc:2670)
FAIL: gcc.dg/torture/vshuf-v8hi.c   -O2  (internal compiler error: in
extract_constrain_insn, at recog.cc:2670)
FAIL: gcc.target/arm/mve/intrinsics/mve_immediates_1_n.c (internal compiler
error: in extract_constrain_insn, at recog.cc:2670)

[Bug target/104790] [12 Regression] ICE (insn does not satisfy its constraints) with MVE since r12-4374-g5efeaa0d29525fa28e189e6278c1b1651fb0d7bf

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104790

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |12.0

[Bug target/104790] [12 Regression] ICE (insn does not satisfy its constraints) with MVE since r12-4374-g5efeaa0d29525fa28e189e6278c1b1651fb0d7bf

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104790

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Andre Simoes Dias Vieira
<avieira@gcc.gnu.org>:

https://gcc.gnu.org/g:796f5220c808bc37adbd1081476589ab1a5d7ac3

commit r12-7538-g796f5220c808bc37adbd1081476589ab1a5d7ac3
Author: Andre Vieira <andre.simoesdiasvieira@arm.com>
Date:   Tue Mar 8 17:46:40 2022 +0000

    arm: MVE: Relax addressing modes for full loads and stores

    This patch relaxes the addressing modes for the mve full load and stores
(by
    full loads and stores I mean non-widening or narrowing loads and stores
resp).
    The code before was requiring a LO_REGNUM for these, where this is only a
    requirement if the load is widening or the store narrowing.

    gcc/ChangeLog:

            PR target/104790
            * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO.
            * config/arm/arm.cc (mve_vector_mem_operand): Relax constraint on
base
            register for non widening loads or narrowing stores.

[Bug target/104790] [12 Regression] ICE (insn does not satisfy its constraints) with MVE since r12-4374-g5efeaa0d29525fa28e189e6278c1b1651fb0d7bf

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104790

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
           Priority|P3                          |P1
         Resolution|---                         |FIXED

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
Fixed I assume.