From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id CB7A83857BB0; Thu, 4 Jan 2024 10:50:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CB7A83857BB0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1704365458; bh=2dplaQKfpaNsouqeURv812oYu0nF68fJCdDAUFNVfbo=; h=From:To:Subject:Date:In-Reply-To:References:From; b=Qc5c+spYrHVy6T2dC9lMKYe65P+8M9X+2vwnkJ4/bQVLSHSMXndAC9ZrdQdI5VG1L xkFztlvnEip+VDR2saLkO8M919w0k8hfq89sCoBfhAZAdEG9ZNGfhz5ywptxVXnC4l QqRKGlVMv9wDdw1kY78XmXULe6CWRDUJnatPmeUo= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/104914] [MIPS] wrong comparison with scrabbled int value Date: Thu, 04 Jan 2024 10:50:52 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104914 --- Comment #25 from GCC Commits --- The master branch has been updated by Roger Sayle : https://gcc.gnu.org/g:3ac58063114cf491891072be6205d32a42c6707d commit r14-6915-g3ac58063114cf491891072be6205d32a42c6707d Author: Roger Sayle Date: Thu Jan 4 10:49:33 2024 +0000 Improved RTL expansion of field assignments into promoted registers. This patch fixes PR rtl-optmization/104914 by tweaking/improving the way the fields are written into a pseudo register that needs to be kept sign extended. The motivating example from the bugzilla PR is: extern void ext(int); void foo(const unsigned char *buf) { int val; ((unsigned char*)&val)[0] =3D *buf++; ((unsigned char*)&val)[1] =3D *buf++; ((unsigned char*)&val)[2] =3D *buf++; ((unsigned char*)&val)[3] =3D *buf++; if(val > 0) ext(1); else ext(0); } which at the end of the tree optimization passes looks like: void foo (const unsigned char * buf) { int val; unsigned char _1; unsigned char _2; unsigned char _3; unsigned char _4; int val.5_5; [local count: 1073741824]: _1 =3D *buf_7(D); MEM[(unsigned char *)&val] =3D _1; _2 =3D MEM[(const unsigned char *)buf_7(D) + 1B]; MEM[(unsigned char *)&val + 1B] =3D _2; _3 =3D MEM[(const unsigned char *)buf_7(D) + 2B]; MEM[(unsigned char *)&val + 2B] =3D _3; _4 =3D MEM[(const unsigned char *)buf_7(D) + 3B]; MEM[(unsigned char *)&val + 3B] =3D _4; val.5_5 =3D val; if (val.5_5 > 0) goto ; [59.00%] else goto ; [41.00%] [local count: 633507681]: ext (1); goto ; [100.00%] [local count: 440234144]: ext (0); [local count: 1073741824]: val =3D{v} {CLOBBER(eol)}; return; } Here four bytes are being sequentially written into the SImode value val. On some platforms, such as MIPS64, this SImode value is kept in a 64-bit register, suitably sign-extended. The function expand_assignm= ent contains logic to handle this via SUBREG_PROMOTED_VAR_P (around line 62= 64 in expr.cc) which outputs an explicit extension operation after each store_field (typically insv) to such promoted/extended pseudos. The first observation is that there's no need to perform sign extension after each byte in the example above; the extension is only required after changes to the most significant byte (i.e. to a field that overla= ps the most significant bit). The bug fix is actually a bit more subtle, but at this point during code expansion it's not safe to use a SUBREG when sign-extending this field. Currently, GCC generates (sign_extend:DI (subreg:SI (reg:DI) 0)) but combine (and other RTL optimizers) later realize that because SImode values are always sign-extended in their 64-bit hard registers that this is a no-op and eliminates it. The trouble is that it's unsafe to refer to the SImode lowpart of a 64-bit register using SUBREG at those critical points when temporarily the value isn't correctly sign-extende= d, and the usual backend invariants don't hold. At these critical points, the middle-end needs to use an explicit TRUNCATE rtx (as this isn't a TRULY_NOOP_TRUNCATION), so that the explicit sign-extension looks like (sign_extend:DI (truncate:SI (reg:DI)), which avoids the problem. 2024-01-04 Roger Sayle Jeff Law gcc/ChangeLog PR rtl-optimization/104914 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_V= AR_P a sign or zero extension is only required if the modified field overlaps the SUBREG's most significant bit. On MODE_REP_EXTEND= ED targets, don't refer to the temporarily incorrectly extended va= lue using a SUBREG, but instead generate an explicit TRUNCATE rtx.=