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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/104921] aarch64: Assembler failure with
 vbfmlalbq_lane_f32 intrinsic
Date: Fri, 09 Dec 2022 22:54:05 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D104921

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
The following patterns has the same problem too:
(define_insn "aarch64_bfdot_lane<VBF:isquadop><VDQSF:mode>"
  [(set (match_operand:VDQSF 0 "register_operand" "=3Dw")
        (plus:VDQSF
          (unspec:VDQSF
           [(match_operand:<VDQSF:VBFMLA_W> 2 "register_operand" "w")
            (match_operand:VBF 3 "register_operand" "w")
            (match_operand:SI 4 "const_int_operand" "n")]
            UNSPEC_BFDOT)
          (match_operand:VDQSF 1 "register_operand" "0")))]
  "TARGET_BF16_SIMD"
{
  int nunits =3D GET_MODE_NUNITS (<VBF:MODE>mode).to_constant ();
  int lane =3D INTVAL (operands[4]);
  operands[4] =3D gen_int_mode (ENDIAN_LANE_N (nunits / 2, lane), SImode);
  return "bfdot\t%0.<VDQSF:Vtype>, %2.<VDQSF:Vbfdottype>, %3.2h[%4]";
}
  [(set_attr "type" "neon_dot<VDQSF:q>")]

That is operand 3 should be using "x" constraint.=