From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id A73BD3858405; Sun, 3 Apr 2022 19:56:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A73BD3858405 From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/105123] [9/10/11/12 Regression] wrong code with -m32 -mtune=i686 and __builtin_shuffle() Date: Sun, 03 Apr 2022 19:56:25 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: jakub at gcc dot gnu.org X-Bugzilla-Target-Milestone: 9.5 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Apr 2022 19:56:25 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105123 --- Comment #6 from CVS Commits --- The releases/gcc-11 branch has been updated by Jakub Jelinek : https://gcc.gnu.org/g:ecc6450668326e52d019b3c298f2c61734ee32c2 commit r11-9755-gecc6450668326e52d019b3c298f2c61734ee32c2 Author: Jakub Jelinek Date: Sun Apr 3 21:50:43 2022 +0200 i386: Fix up ix86_expand_vector_init_general [PR105123] The following testcase is miscompiled on ia32. The problem is that at -O0 we end up with: vector(4) short unsigned int _1; short unsigned int u.0_3; ... _1 =3D {u.0_3, u.0_3, u.0_3, u.0_3}; statement (dead) which is wrongly expanded. elt is (subreg:HI (reg:SI 83 [ u.0_3 ]) 0), tmp_mode SImode, so after convert_mode we start with word (reg:SI 83 [ u.0_3 ]). The intent is to manually broadcast that value to 2 SImode parts, but because we pass word as target to expand_simple_binop, it will overwrite (reg:SI 83 [ u.0_3 ]) and we end up with 0: 10: {r83:SI=3Dr83:SI<<0x10;clobber flags:CC;} 11: {r83:SI=3Dr83:SI|r83:SI;clobber flags:CC;} 12: {r83:SI=3Dr83:SI<<0x10;clobber flags:CC;} 13: {r83:SI=3Dr83:SI|r83:SI;clobber flags:CC;} 14: clobber r110:V4HI 15: r110:V4HI#0=3Dr83:SI 16: r110:V4HI#4=3Dr83:SI as the two ors do nothing and two shifts each by 16 left shift it all away. The following patch fixes that by using NULL_RTX target, so we expand i= t as 10: {r110:SI=3Dr83:SI<<0x10;clobber flags:CC;} 11: {r111:SI=3Dr110:SI|r83:SI;clobber flags:CC;} 12: {r112:SI=3Dr83:SI<<0x10;clobber flags:CC;} 13: {r113:SI=3Dr112:SI|r83:SI;clobber flags:CC;} 14: clobber r114:V4HI 15: r114:V4HI#0=3Dr111:SI 16: r114:V4HI#4=3Dr113:SI instead. Another possibility would be to pass NULL_RTX only when word =3D=3D elt and word otherwise, where word would necessarily be a pseudo from the f= irst shift after passing NULL_RTX there once or pass NULL_RTX for the shift = and word for ior. 2022-04-03 Jakub Jelinek PR target/105123 * config/i386/i386-expand.c (ix86_expand_vector_init_general): Avoid using word as target for expand_simple_binop when doing ASHIFT = and IOR. * gcc.target/i386/pr105123.c: New test. (cherry picked from commit e1a74058b784c845e84a0cf1997b54b984df483d)=