[Bug target/105136] [11/12 regression] Missed optimization regression with 32-bit adds and shifts

["ubizjak at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105136

--- Comment #2 from Uroš Bizjak <ubizjak at gmail dot com> ---
The regression in bar: is due to RA regression for:

(insn 28 27 29 2 (parallel [
            (set (reg:SI 89)
                (plus:SI (reg:SI 92)
                    (subreg:SI (reg:DI 87) 0)))
            (clobber (reg:CC 17 flags))
        ]) "pr105136.c":4:11 229 {*addsi_1}
     (expr_list:REG_DEAD (reg:SI 92)
        (expr_list:REG_UNUSED (reg:CC 17 flags)
            (nil))))

gcc-10.3 allocates:

(insn 28 27 29 2 (parallel [
            (set (reg:SI 0 ax [89])
                (plus:SI (reg:SI 4 si [92])
                    (reg:SI 5 di [87])))
            (clobber (reg:CC 17 flags))
        ]) "pr105136.c":4:11 185 {*addsi_1}
     (nil))

while gcc-12 allocates:

(insn 28 27 29 2 (parallel [
            (set (reg:SI 4 si [89])
                (plus:SI (reg:SI 4 si [92])
                    (reg:SI 5 di [87])))
            (clobber (reg:CC 17 flags))
        ]) "pr105136.c":4:11 229 {*addsi_1}
     (nil))

(...)

and reloads the output to ax:

(insn 35 29 30 2 (set (reg:SI 0 ax [89])
        (reg:SI 4 si [89])) "pr105136.c":4:11 81 {*movsi_internal}
     (nil))
(insn 30 35 20 2 (set (reg:SI 0 ax [89])
        (if_then_else:SI (eq (reg:CCZ 17 flags)
                (const_int 0 [0]))
            (reg:SI 5 di [87])
            (reg:SI 0 ax [89]))) "pr105136.c":4:11 1201 {*movsicc_noc}
     (nil))

The pattern allows r/r/r in alternative 3, so the question is why RA doesn't
consider it:

(define_insn "*add<mode>_1"
  [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r,r")
        (plus:SWI48
          (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r")
          (match_operand:SWI48 2 "x86_64_general_operand" "re,BM,0,le")))
   (clobber (reg:CC FLAGS_REG))]

The "l" constraint is user defined register constraint:

(define_register_constraint "l" "INDEX_REGS"
 "@internal Any register that can be used as the index in a base+index
  memory access: that is, any general register except the stack pointer.")

so perhaps user defined constraint deters RA from using this alternative.