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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug middle-end/105137] Missed optimization 64-bit adds and shifts
Date: Sun, 01 Jan 2023 17:01:39 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105137

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Roger Sayle <sayle@gcc.gnu.org>:

https://gcc.gnu.org/g:4f1314f547f69d3a2b1f16ce301267e3bfb4e427

commit r13-4945-g4f1314f547f69d3a2b1f16ce301267e3bfb4e427
Author: Roger Sayle <roger@nextmovesoftware.com>
Date:   Sun Jan 1 17:00:28 2023 +0000

    Add post-reload splitter for extendditi2 on x86_64.

    This is another step towards a possible solution for PR 105137.
    This patch introduces a define_insn for extendditi2 that allows
    DImode to TImode sign-extension to be represented in the early
    RTL optimizers, before being split post-reload into the exact
    same idiom as currently produced by RTL expansion.

    Typically this produces the identical code, so the first new
    test case:
    __int128 foo(long long x) { return (__int128)x; }

    continues to generate:
    foo:    movq    %rdi, %rax
            cqto
            ret

    The "magic" is that this representation allows combine and the
    other RTL optimizers to do a better job.  Hence, the second
    test case:

    __int128 foo(__int128 a, long long b) {
        a +=3D ((__int128)b) << 70;
        return a;
    }

    which mainline with -O2 currently generates as:

    foo:    movq    %rsi, %rax
            movq    %rdx, %rcx
            movq    %rdi, %rsi
            salq    $6, %rcx
            movq    %rax, %rdi
            xorl    %eax, %eax
            movq    %rcx, %rdx
            addq    %rsi, %rax
            adcq    %rdi, %rdx
            ret

    with this patch now becomes:
    foo:    movl    $0, %eax
            salq    $6, %rdx
            addq    %rdi, %rax
            adcq    %rsi, %rdx
            ret

    i.e. the same code for the signed and unsigned extension variants.

    2023-01-01  Roger Sayle  <roger@nextmovesoftware.com>
                Uro=C3=85=C2=A1 Bizjak  <ubizjak@gmail.com>

    gcc/ChangeLog
            * config/i386/i386.md (extendditi2): New define_insn.
            (define_split): Use DWIH mode iterator to treat new extendditi2
            identically to existing extendsidi2_1.
            (define_peephole2): Likewise.
            (define_peephole2): Likewise.
            (define_Split): Likewise.

    gcc/testsuite/ChangeLog
            * gcc.target/i386/extendditi2-1.c: New test case.
            * gcc.target/i386/extendditi2-2.c: Likewise.=