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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug tree-optimization/105175] [12 Regression] Pointless warning
 about missed vector optimization
Date: Wed, 06 Apr 2022 08:17:21 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105175

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|rtl-optimization            |tree-optimization
   Last reconfirmed|                            |2022-04-06
   Target Milestone|---                         |12.0
             Target|                            |x86_64-*-*
             Status|UNCONFIRMED                 |ASSIGNED
           Keywords|                            |diagnostic,
                   |                            |missed-optimization
     Ever confirmed|0                           |1

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
I think the issue is that the vectorizer generates

   <bb 2> [local count: 1073741824]:
+  vect__1.5_8 =3D MEM <vector(2) unsigned int> [(unsigned int
*)&qemuMigrationCookieGetPersistent_mig];
+  vect__2.6_9 =3D vect__1.5_8 & { 1, 1 };
   _1 =3D qemuMigrationCookieGetPersistent_mig.flags;
   _2 =3D _1 & 1;
-  qemuMigrationCookieGetPersistent_mig.flags =3D _2;
   _3 =3D qemuMigrationCookieGetPersistent_mig.flagsMandatory;
   _4 =3D _3 & 1;
-  qemuMigrationCookieGetPersistent_mig.flagsMandatory =3D _4;
+  MEM <vector(2) unsigned int> [(unsigned int
*)&qemuMigrationCookieGetPersistent_mig] =3D vect__2.6_9;

but appearantly it does not check availability of the bitwise AND V2SImode
operation.  vector lowering recognizes this missing operation and lowers
it to

+  long unsigned int _6;
+  long unsigned int _7;
+  vector(2) unsigned int _11;

   <bb 2> [local count: 1073741824]:
   vect__1.5_8 =3D MEM <vector(2) unsigned int> [(unsigned int
*)&qemuMigrationCookieGetPersistent_mig];
-  vect__2.6_9 =3D vect__1.5_8 & { 1, 1 };
+  _7 =3D VIEW_CONVERT_EXPR<long unsigned int>(vect__1.5_8);
+  _6 =3D _7 & 4294967297;
+  _11 =3D VIEW_CONVERT_EXPR<vector(2) unsigned int>(_6);
+  vect__2.6_9 =3D _11;

_maybe_ V2SImode is also a real thing now even with -mno-sse, but the
AND is cut out (or not implemented).

That is, this is probably a vectorizer missed target check.=