From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 90C7B3858D3C; Wed, 20 Apr 2022 07:44:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 90C7B3858D3C From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/105312] [12 Regression] ICE in gimple_expand_vec_cond_expr on arm-linux since r12-834-ga6eacbf1055520 Date: Wed, 20 Apr 2022 07:44:31 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 12.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Apr 2022 07:44:31 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105312 --- Comment #2 from Richard Biener --- Confirmed. _37 =3D vect_vec_iv_.13_32 =3D=3D { 0, 0, 0, 0 }; vect_iftmp.14_38 =3D VEC_COND_EXPR <_37, { 1.0e+0, 1.0e+0, 1.0e+0, 1.0e+0 }= , { 0.0, 0.0, 0.0, 0.0 }>; (gdb) p debug_tree (op0) unit-size align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-ty= pe 0x7ffff64317e0 precision:32 min max > V4SI size unit-size align:64 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7ffff6431888 nunits:4> visited def_stmt _37 =3D vect_vec_iv_.13_32 =3D=3D { 0, 0, 0, 0 }; version:37> we can't do VCONDEQ, we _can_ compute op0 but do not have vcond_mask which we assume here. So this is a mismatch between ISEL and vector lowering or alternatively a failure to - for non-mask vectors - provide a fallback via masking. For vcond_mask I see there is v2sfv2si but no v4sfv4si, so not sure whether this can be tackled on the backend side. Note for a masking fallback we'd have to ensure support for integer mode bitwise ops as well as view-converting V4SF to and from V4SI. There is /* Lower mask typed, non-vector mode VEC_COND_EXPRs to bitwise operations. Those can end up generated by folding and at least for integer mode ma= sks we cannot expect vcond expanders to exist. We lower a ? b : c to (b & a) | (c & ~a). */ if (VECTOR_BOOLEAN_TYPE_P (TREE_TYPE (lhs)) && !VECTOR_MODE_P (mode)) { gcc_assert (types_compatible_p (TREE_TYPE (op0), TREE_TYPE (op1))); gimple_seq stmts =3D NULL; tree type =3D TREE_TYPE (lhs); location_t loc =3D gimple_location (stmt); tree tem0 =3D gimple_build (&stmts, loc, BIT_AND_EXPR, type, op1, op0= ); tree tem1 =3D gimple_build (&stmts, loc, BIT_NOT_EXPR, type, op0); tree tem2 =3D gimple_build (&stmts, loc, BIT_AND_EXPR, type, op2, tem= 1); tree tem3 =3D gimple_build (&stmts, loc, BIT_IOR_EXPR, type, tem0, te= m2); gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT); return gimple_build_assign (lhs, tem3); } but as said the immediate failure is that veclower thinks we can handle _37 =3D vect_vec_iv_.13_32 =3D=3D { 0, 0, 0, 0 }; vect_iftmp.14_38 =3D VEC_COND_EXPR <_37, { 1.0e+0, 1.0e+0, 1.0e+0, 1.0e+0= }, { 0.0, 0.0, 0.0, 0.0 }>; but ISEL thinks we cannot. I will look into that.=