From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 08D223858D1E; Tue, 26 Apr 2022 08:12:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 08D223858D1E From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug rtl-optimization/105314] [12 Regression] ifcvt regression in noce_try_store_flag_mask Date: Tue, 26 Apr 2022 08:12:44 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: rtl-optimization X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 12.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Apr 2022 08:12:45 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105314 --- Comment #9 from CVS Commits --- The master branch has been updated by Jakub Jelinek : https://gcc.gnu.org/g:7d31c678d68d7b6820a958584619ca763b0eb9c5 commit r12-8264-g7d31c678d68d7b6820a958584619ca763b0eb9c5 Author: Jakub Jelinek Date: Tue Apr 26 10:11:58 2022 +0200 ifcvt: Improve noce_try_store_flag_mask [PR105314] The following testcase regressed on riscv due to the splitting of criti= cal edges in the sink pass, similarly to x86_64 compared to GCC 11 we now s= wap the edges, whether true or false edge goes to an empty forwarded bb. From GIMPLE POV, those 2 forms are equivalent, but as can be seen here,= for some ifcvt opts it matters one way or another. On this testcase, noce_try_store_flag_mask used to trigger and transfor= med if (pseudo2) pseudo1 =3D 0; into pseudo1 &=3D -(pseudo2 =3D=3D 0); But with the swapped edges ifcvt actually sees if (!pseudo2) pseudo3 =3D pseudo1; else pseudo3 =3D 0; and noce_try_store_flag_mask punts. IMHO there is no reason why it should punt those, it is equivalent to pseudo3 =3D pseudo1 & -(pseudo2 =3D=3D 0); and especially if the target has 3 operand AND, it shouldn't be any more costly (and even with 2 operand AND, it might very well happen that RA can make it happen without any extra moves). Initially I've just removed the rtx_equal_p calls from the conditions and didn't add anything there, but that broke aarch64 bootstrap and regressed some testcases on x86_64, where if_info->a or if_info->b coul= d be some larger expression that we can't force into a register. Furthermore, the case where both if_info->a and if_info->b are constant= s is better handled by other ifcvt optimizations like noce_try_store_flag or noce_try_inverse_constants or noce_try_store_flag_constants. So, I've restricted it to just a REG (perhaps SUBREG of REG might be ok too) next to what has been handled previously. 2022-04-26 Jakub Jelinek PR rtl-optimization/105314 * ifcvt.cc (noce_try_store_flag_mask): Don't require that the non-zero operand is equal to if_info->x, instead use the non-zero operand as one of the operands of AND with if_info->x as target. * gcc.target/riscv/pr105314.c: New test.=