From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 7D0543856DD6; Wed, 5 Jul 2023 16:46:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7D0543856DD6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1688575565; bh=yZTHu9Yc5mvnYuiI4dROvZb0LSuGvP0v3r86xzr2Lz8=; h=From:To:Subject:Date:In-Reply-To:References:From; b=GZpXE2GwAq40mzCIUpAe4g6Y/eiBwe4RsDJmPODRwq0yi9rj5iQd5xjU2Wd67qC6i L4Jsej+zu6VKi3FtTpsNoR78YdVcTiJn5gyYBz2nq/lauP7GPpV5GHSdMranjULemw CCdQfP8AFtbjMONRHVG2FlpvMvV+DPINPpgkkgxw= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/105325] power10: Error: operand out of range Date: Wed, 05 Jul 2023 16:46:04 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 11.2.0 X-Bugzilla-Keywords: assemble-failure X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: ASSIGNED X-Bugzilla-Resolution: X-Bugzilla-Priority: P1 X-Bugzilla-Assigned-To: meissner at gcc dot gnu.org X-Bugzilla-Target-Milestone: 13.2 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105325 --- Comment #18 from CVS Commits --- The releases/gcc-13 branch has been updated by Michael Meissner : https://gcc.gnu.org/g:68aa17cff9279d2f3acebaf4d5cb9ababe743046 commit r13-7535-g68aa17cff9279d2f3acebaf4d5cb9ababe743046 Author: Michael Meissner Date: Wed Jul 5 12:44:55 2023 -0400 Fix power10 fusion bug with prefixed loads, PR target/105325 This changes fixes PR target/105325. PR target/105325 is a bug where an invalid lwa instruction is generated due to power10 fusion of a load instruction to a GPR and an compare immediate instruction with the immediate being -1, 0, or 1. In some cases, when the load instruction is done, the GCC compiler would generate a load instruction with an offset that was too large to fit in= to the normal load instruction. In particular, loads from the stack might originally have a small offse= t, so that the load is not a prefixed load. However, after the stack is set = up, and register allocation has been done, the offset now is large enough that = we would have to use a prefixed load instruction. The support for prefixed loads did not consider that patterns with a fu= sed load and compare might have a prefixed address. Without this support, the proper prefixed load won't be generated. In the original code, when the split2 pass is run after reload has fini= shed the ds_form_mem_operand predicate that was used for lwa and ld no longer returns true. When the pattern was created, ds_form_mem_operand recognized the insn as being valid since the offset was small. But after register allocation, ds_form_mem_operand did not return true. Because it didn't return true, the insn could not be split. Since the insn was not split and the prefix support did not indicate a prefixed instruction was used, the wrong load is generated. The solution involves: 1) Don't use ds_form_mem_operand for ld and lwa, always use non_update_memory_operand. 2) Delete ds_form_mem_operand since it is no longer used. 3) Use the "YZ" constraints for ld/lwa instead of "m". 4) If we don't need to sign extend the lwa, convert it to lwz, and= use cmpwi instead of cmpdi. Adjust the insn name to reflect the co= de generate. 5) Insure that the insn using lwa will be recognized as having a prefixed operand (and hence the insn length will be 16 bytes instead of 8 bytes). 5a) Set the prefixed and maybe_prefix attributes to know that fused_load_cmpi are also load insns; 5b) In the case where we are just setting CC and not using the memory afterward, set the clobber to use a DI register, and put an explicit sign_extend operation in the split; 5c) Set the sign_extend attribute to "yes" for lwa. 5d) 5a-5c are the things that prefixed_load_p in rs6000.cc chec= ks to ensure that lwa is treated as a ds-form instruction and not= as a d-form instruction (i.e. lwz). 6) Add a new test case for this case. 7) Adjust the insn counts in fusion-p10-ldcmpi.c. Because we are = no longer using ds_form_mem_operand, the ld and lwa instructions w= ill fuse x-form (reg+reg) addresses in addition ds-form (reg+offset or r= eg). 2023-06-23 Michael Meissner gcc/ PR target/105325 * config/rs6000/genfusion.pl (gen_ld_cmpi_p10_one): Fix problems that allowed prefixed lwa to be generated. * config/rs6000/fusion.md: Regenerate. * config/rs6000/predicates.md (ds_form_mem_operand): Delete. * config/rs6000/rs6000.md (prefixed attribute): Add support for load plus compare immediate fused insns. (maybe_prefixed): Likewise. gcc/testsuite/ PR target/105325 * g++.target/powerpc/pr105325.C: New test. * gcc.target/powerpc/fusion-p10-ldcmpi.c: Update insn counts. (cherry picked from commit 370de1488a9a49956c47e5ec8c8f1489b4314a34) Co-Authored-By: Aaron Sawdey =